參數(shù)資料
型號： PIC18LF452T-I/L
廠商： Microchip Technology
文件頁數(shù)： 63/134頁
文件大小： 0K
描述： IC MCU FLASH 16KX16 A/D 44PLCC
產(chǎn)品培訓模塊： Asynchronous Stimulus
標準包裝： 500
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 帶卷 (TR)
Micrel, Inc.
KSZ8864RMN
April 2012
34
M9999-043012-1.5
Figure 6. 802.1p Priority Field Format
802.1p-based priority is enabled by bit [5] of the port registers control 0 for Ports 1 and 2, respectively.
The KSZ8864RMN provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field (TCI), is
also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion
is enabled by bit [2] of the port registers control 0 and the port register control 8 to select which source port
(ingress port) PVID can be inserted on the egress port for Ports 1, 2, 3 and 4, respectively. At the egress port, untagged
packets are tagged with the ingress port’s default tag. The default tags are programmed in the port registers control 3 and
control 4 for ports 1,2,3 and 4, respectively. The KSZ8864RMN will not add tags to already tagged packets.
Tag Removal
is enabled by bit [1] of the port registers control 0 for Ports 1, 2, 3 and 4, respectively. At the egress port,
tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8864RMN will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping
is a QoS feature that allows the KSZ8864RMN to set the “User Priority Ceiling” at any
ingress port by the port register control 2 bit 7. If the ingress packet’s priority field has a higher priority value than the
default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 144 to 159) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities of DSCP decoded is compared with the corresponding bits in the DSCP
register to determine priority.
Spanning Tree Support
Port 4 is the designated port for spanning tree support.
The other ports (Port 1 – Port 3) can be configured in one of the five spanning tree states via “transmit enable,” “receive
enable,” and “l(fā)earning disable” register settings in Registers 34, 50 for Ports 1, 2 and 3, respectively. The following
description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard
those packets. Note: processor is connected to Port 4 through MAC4 SW4-MII/RMII interface. Address learning is
disabled on the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
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