參數(shù)資料
型號: PIC18LF452T-I/L
廠商: Microchip Technology
文件頁數(shù): 59/134頁
文件大小: 0K
描述: IC MCU FLASH 16KX16 A/D 44PLCC
產(chǎn)品培訓模塊: Asynchronous Stimulus
標準包裝: 500
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8864RMN
April 2012
30
M9999-043012-1.5
Please see the pins [47, 48] description for detail configuration for the MAC mode and PHY mode of the port 4 MAC4
SW4-MII, the default is SW4-MII with PHY mode. Please see the strap pin P2LED0 and the register 223 bit 6 for the MAC
mode and PHY mode of the port 3 MAC3 SW3-MII, the default is SW3-MII with PHY mode also.
KSZ8864RMN PHY Mode Connection
KSZ8864RMN MAC Mode Connection
External
MAC
KSZ8864RMN
SW3/4-MII Signals
Type
Description
External
PHY
KSZ8864RMN
SW3/4-MII Signals
Type
MTXEN
SMxTXEN
Input
Transmit enable
MTXEN
SMxRXDV
Output
MTXD3
SMxTXD[3]
Input
Transmit data bit 3
MTXD3
SMxRXD[3]
Output
MTXD2
SMxTXD[2]
Input
Transmit data bit 2
MTXD2
SMxRXD[2]
Output
MTXD1
SMxTXD[1]
Input
Transmit data bit 1
MTXD1
SMxRXD[1]
Output
MTXD0
SMxTXD[0]
Input
Transmit data bit 0
MTXD0
SMxRXD[0]
Output
MTXC
SMxTXC
Output
Transmit clock
MTXC
SMxRXC
Input
MCOL
SMxCOL
Output
Collision detection
MCOL
SMxCOL
Input
MCRS
SMxCRS
Output
Carrier sense
MCRS
SMxCRS
Input
MRXDV
SMxRXDV
Output
Receive data valid
MRXDV
SMxTXEN
Input
MRXD3
SMxRXD[3]
Output
Receive data bit 3
MRXD3
SMxTXD[3]
Input
MRXD2
SMxRXD[2]
Output
Receive data bit 2
MRXD2
SMxTXD[2]
Input
MRXD1
SMxRXD[1]
Output
Receive data bit 1
MRXD1
SMxTXD[1]
Input
MRXD0
SMxRXD[0]
Output
Receive data bit 0
MRXD0
SMxTXD[0]
Input
MRXC
SMxRXC
Output
Receive clock
MRXC
SMxTXC
Input
Note
:
‘x’ is 3 or 4 for SW3 or SW4 in the table.
Table 3. Switch MAC 3 SW3-MII and MAC 4 SW4-MII Signals
The switch MII interface operates in either MAC mode or PHY mode for KSZ8864RMN. These interfaces are nibble-wide
data interfaces and therefore run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side
indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that
convey when the data is valid and without physical layer errors. For half-duplex operation, there is a signal that indicates a
collision has occurred during transmission.
Note that the signal MRXER is not provided on the SWx-MII interface and the signal MTXER is not provided on the SWx-
MII interface for both PHY and MAC mode operation. Normally MRXER would indicate a receive error coming from the
physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for
this configuration. For PHY mode operation, if the device interfacing with the KSZ8864RMN has an MRXER pin, it should
be tied low. For MAC mode operation, if the device interfacing with the KSZ8864RMN has an MTXER pin, it should be
tied low.
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