參數(shù)資料
型號： PIC18LF452T-I/L
廠商： Microchip Technology
文件頁數(shù)： 92/134頁
文件大?。?/td> 0K
描述： IC MCU FLASH 16KX16 A/D 44PLCC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 500
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 帶卷 (TR)
PIC16C9XX
DS30444E - page 60
1997 Microchip Technology Inc.
10.3.2
PWM DUTY CYCLE
The PWM duty cycle is specied by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and CCP1CON<5:4> contains the two
LSbs.
This
10-bit
value
is
represented
by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>)
Tosc (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM fre-
quency:
Note:
The Timer2 postscaler (Section 9.0) is not
used in the determination of the PWM fre-
quency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
Note:
If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
log
(
FPWM
log(2)
FOSC
)
bits
=
EXAMPLE 10-2: PWM PERIOD AND DUTY
CYCLE CALCULATION
Desired PWM frequency is 31.25 kHz,
Fosc = 8 MHz
TMR2 prescale = 1
1/31.25 kHz
= [ (PR2) + 1 ] 4 1/8 MHz 1
32
s
= [ (PR2) + 1 ] 4 125 ns 1
PR2
= 63
Find the maximum resolution of the duty cycle that can
be used with a 31.25 kHz frequency and 8 MHz oscilla-
tor:
1/31.25 kHz
= 2
PWM RESOLUTION 1/8 MHz 1
32
s
= 2
PWM RESOLUTION 125 ns 1
256
= 2
PWM RESOLUTION
log(256)
= (PWM Resolution) log(2)
8.0
= PWM Resolution
At most, an 8-bit resolution duty cycle can be obtained
from a 31.25 kHz frequency and a 8 MHz oscillator, i.e.,
0
≤ CCPR1L:CCP1CON<5:4> ≤ 255. Any value greater
than 255 will result in a 100% duty cycle.
In order to achieve higher resolution, the PWM fre-
quency must be decreased. In order to achieve higher
PWM frequency, the resolution must be decreased.
Table 10-2 lists example PWM frequencies and resolu-
tions for Fosc = 8 MHz. TMR2 prescaler and PR2 val-
ues are also shown.
10.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when conguring
the CCP module for PWM operation:
1.
Set the PWM period by writing to the PR2 regis-
ter.
2.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5.
Congure the CCP module for PWM operation.
TABLE 10-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 8 MHz
PWM Frequency
488 Hz
1.95 kHz
7.81 kHz
31.25 kHz
62.5 kHz
250 kHz
Timer Prescaler (1, 4, 16)
16
4
1
PR2 Value
0xFF
0x3F
0x1F
0x07
Maximum Resolution (bits)
10
8
7
5
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