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PIC16F87X
DS30292B-page 16
1999 Microchip Technology Inc.
Bank 1
80h
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
81h
OPTION_R
EG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
82h
(4)
83h
(4)
84h
(4)
85h
86h
87h
88h
(5)
89h
(5)
8Ah
(1,4)
8Bh
(4)
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
0000 0000
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
TRISA
TRISB
TRISC
—
—
PORTA Data Direction Register
--11 1111
--11 1111
PORTB Data Direction Register
PORTC Data Direction Register
1111 1111
1111 1111
1111 1111
1111 1111
TRISD
PORTD Data Direction Register
1111 1111
1111 1111
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
0000 -111
0000 -111
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
PSPIE
(3)
—
—
Unimplemented
Unimplemented
GCEN
Timer2 Period Register
Synchronous Serial Port (I
2
C mode) Address Register
SMP
CKE
Unimplemented
Unimplemented
Unimplemented
CSRC
TX9
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low Byte
ADFM
—
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6:
PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
8Dh
8Eh
8Fh
90h
91h
92h
PIE2
PCON
—
—
SSPCON2
PR2
(6)
—
—
—
EEIE
—
BCLIE
—
—
—
—
CCP2IE
BOR
-r-0 0--0
-r-0 0--0
POR
---- --qq
—
—
---- --uu
—
—
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
0000 0000
1111 1111
1111 1111
93h
SSPADD
0000 0000
0000 0000
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
SSPSTAT
—
—
—
TXSTA
SPBRG
—
—
—
—
ADRESL
ADCON1
D/A
P
S
R/W
UA
BF
0000 0000
—
—
—
0000 0000
—
—
—
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
—
—
—
—
0000 0000
—
—
—
—
xxxx xxxx
uuuu uuuu
—
—
PCFG3
PCFG2
PCFG1
PCFG0
0--- 0000 0--- 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addres
s
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)