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| 型號(hào)： | PIC876 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 28/40-pin 8-Bit CMOS FLASH Microcontrollers |
| 中文描述： | 28/40-pin 8位CMOS閃存微控制器 |
| 文件頁(yè)數(shù)： | 41/200頁(yè) |
| 文件大?。?/td> | 3544K |
| 代理商： | PIC876 |
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1999 Microchip Technology Inc.
DS30292B-page 41
PIC16F87X
4.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire V
DD
range. A bulk erase operation may not be
issued from user code (which includes removing code
protection). The data memory is not directly mapped in
the register file space. Instead it is indirectly addressed
through the Special Function Registers (SFR).
There are six SFRs used to read and write the program
and data EEPROM memory. These registers are:
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. The
registers EEDATH and EEADRH are not used for data
EEPROM access. These devices have up to 256 bytes
of data EEPROM with an address range from 0h to
FFh.
The EEPROM data memory is rated for high erase/
write cycles. The write time is controlled by an on-chip
timer. The write time will vary with voltage and temper-
ature, as well as from chip-to-chip. Please refer to the
specifications for exact limits.
The program memory allows word reads and writes.
Program memory access allows for checksum calcula-
tion and calibration table storage. A byte or word write
automatically erases the location and writes the new
data (erase before write). Writing to program memory
will cease operation until the write is complete. The pro-
gram memory cannot be accessed during the write,
therefore code cannot execute. During the write opera-
tion, the oscillator continues to clock the peripherals,
and therefore they continue to operate. Interrupt events
will be detected and essentially “queued” until the write
is completed. When the write completes, the next
instruction in the pipeline is executed and the branch to
the interrupt vector address will occur.
When interfacing to the program memory block, the
EEDATH:EEDATA registers form a two byte word,
which holds the 14-bit data for read/write. The
EEADRH:EEADR registers form a two byte word,
which holds the 13-bit address of the EEPROM loca-
tion being accessed. These devices can have up to 8K
words of program EEPROM with an address range
from 0h to 3FFFh. The unused upper bits in both the
EEDATH and EEDATA registers all read as “0’s”.
The value written to program memory does not need to
be a valid instruction. Therefore, up to 14-bit numbers
can be stored in memory for use as calibration param-
eters, serial numbers, packed 7-bit ASCII, etc. Execut-
ing a program memory location containing data that
forms an invalid instruction results in a
NOP
.
4.1
EEADR
The address registers can address up to a maximum of
256 bytes of data EEPROM or up to a maximum of 8K
words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the EEADRH register and
the LSByte is written to the EEADR register. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register.
On the PIC16F873/874 devices with 128 bytes of
EEPROM, the MSbit of the EEADR must always be
cleared to prevent inadvertent access to the wrong
location. This also applies to the program memory. The
upper MSbits of EEADRH must always be clear.
4.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write sequence.
Control bit EEPGD determines if the access will be a
program or a data memory access. When clear, any
subsequent operations will operate on the data mem-
ory. When set, any subsequent operations will operate
on the program memory.
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The value of
the data and address registers and the EEPGD bit
remains unchanged.
Interrupt flag bit EEIF, in the PIR2 register, is set when
write is complete. It must be cleared in software.
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