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RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
37
Figure 3 – Partial Packet Buffer Structure
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
Partial Packet
Buffer RAM
Block 511
Block 0
Block 1
Block 2
Block 3
Block 511
Block 0
Block 1
Block 2
Block 3
Block
Pointer RAM
Block 200
Block 200
0x03
0xC8
0x01
XX
XX
XX
The FIFO algorithm of the partial packet buffer processor is based on a programmable per-
channel transfer size. Instead of tracking the number of full blocks in a channel FIFO, the
processor tracks the number of transactions. Whenever the partial packet writer fills a transfer-
sized number of blocks or writes an end-of-packet flag to the channel FIFO, a transaction is
created. Whenever the partial packet reader transmits a transfer-size number of blocks or an
end-of-packet flag to the RMAC block, a transaction is deleted. Thus, small packets less than the
transfer size will be naturally transferred to the RMAC block without having to precisely track the
number of full blocks in the channel FIFO.
The partial packet roamer performs the transaction accounting for all channel FIFOs. The roamer
increments the transaction count when the writer signals a new transaction and sets a per-
channel flag to indicate a non-zero transaction count. The roamer searches the flags in a round-
robin fashion to decide for which channel FIFO to request transfer by the RMAC block. The
roamer informs the partial packet reader of the channel to process. The reader transfers the data
to the RMAC until the channel transfer size is reached or an end of packet is detected. The
reader then informs the roamer that a transaction is consumed. The roamer updates its
transaction count and clears the non-zero transaction count flag if required. The roamer then
services the next channel with its transaction flag set high.