![](http://datasheet.mmic.net.cn/330000/PM7382-PI_datasheet_16444416/PM7382-PI_308.png)
RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
297
Figure 36 – PCI Target Abort
PCICLK
FRAMEB
1
2
3
4
5
6
T
TRDYB
DEVSELB
STOPB
The PCI Bus Request Cycle Diagram (Figure 37) illustrates the case when the
initiator is requesting the bus from the bus arbiter.
When the FREEDM-32P256 is the initiator, it requests the PCI bus by asserting
its REQB output to the central arbiter. The arbiter grants the bus to the
FREEDM-32P256 by asserting the GNTB line. The FREEDM-32P256 will wait
till both the FRAMEB and IRDYB lines are idle before starting its access on the
PCI bus. The arbiter can remove the GNTB signal at any time, but the
FREEDM-32P256 will complete the current transfer before relinquishing the bus.
Figure 37 – PCI Bus Request Cycle
PCICLK
REQB
1
2
3
4
5
6
T
GNTB
FRAMEB
The PCI Initiator Abort Termination Diagram (Figure 38) illustrates the case when
the initiator aborts a transaction on the PCI bus.
An initiator may terminate a cycle if no target claims it within five clock cycles. A
target may not have responded because it was incapable of dealing with the
request or a bad address was generated by the initiator. IRDYB must be valid
one clock after FRAMEB is deasserted as in a normal cycle. When the
FREEDM-32P256 is the initiator and aborts the transaction, it reports the error
condition to the PCI Host.