RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
50
Figure 7 – RPDRF and RPDRR Queues
RQB[31:2] = Rx Queue Base register
RPDRRQS[15:0] = RPDR Ready Queue Start register
RPDRRQW[15:0] = RPDR Ready Queue Write register
RPDRRQR[15:0] = RPDR Ready Queue Read register
RPDRRQE[15:0] = RPDR Ready Queue End register
Receive Packet Descriptor (RPD) Reference Queues
Base Address:
Index Registers:
Ready Queue:
RPDRSFQS[15:0] = RPDR Small Free Queue Start register
RPDRSFQW[15:0] = RPDR Small Free Queue W rite register
RPDRSFQR[15:0] = RPDR Small Free Queue Read register
RPDRSFQE[15:0] = RPDR Small Free Queue End register
Large Buffer Free Queue:
Small Buffer Free Queue:
RPDRLFQS[15:0] = RPDR Large Free Queue Start register
RPDRLFQW[15:0] = RPDR Large Free Queue Write register
RPDRLFQR[15:0] = RPDR Large Free Queue Read register
RPDRLFQE[15:0] = RPDR Large Free Queue End register
Base Address
+ Index Register
-------------------------
Host Address
00
RQB[31:2]
Index[15:0]
+
AD[31:0]
Rx Packet Descriptor Reference Queue Memory Map
RQB
Bit 0
Bit 31
RPDR
Valid RPDR
256KB
RPD Reference Queues
Host Memory
RPDRRQS
RPDRRQW
RPDRRQR
RPDRRQE
RPDRLFQS
RPDRLFQW
RPDRLFQR
RPDRLFQE
RPDRSFQS
RPDRSFQW
RPDRSFQR
RPDRSFQE
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
00
Status + RPDR
Status + RPDR
Status + RPDR
Status + RPDR
Status + RPDR
Status + RPDR