參數(shù)資料
型號(hào): PowerNP NPe405L
廠商: IBM Microeletronics
英文描述: 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述: 32位嵌入式處理器(32位嵌入式處理器)
文件頁數(shù): 10/48頁
文件大小: 741K
代理商: POWERNP NPE405L
Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
10
IIC Bus Interface
Compliant with Phillips Semiconductors I
2
C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed V
DD
IIC interface
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocol
Programmable error recovery
HDLCEX Interface
Multichannel HDLC controller core
Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 8 Mbps
32 transmit and 32 receive channels
Supports HDLC protocol as well as a Transparent mode
One channel per port, autonomous management of the I-Frame and S-Frame of the Normal Response
mode (NRM) protocol
Software emulation of NRM mode
相關(guān)PDF資料
PDF描述
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