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參數(shù)資料
| 型號(hào)： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 38/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
38
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the NPe405L. This
controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG
is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew
there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When
using an SSCG with the NPe405L the following conditions must be met:
The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
NPe405L with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
The maximum frequency deviation cannot exceed
3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board NPe405L peripherals impose more stringent requirements (see Note 1).
Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
modulation.
Use the SDRAM MemClk since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates. If an external serial clock is used the baud rate is
unaffected by the modulation
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Caution:
It is up to the system designer to ensure that any SSCG used with the NPe405L meets the above
requirements and does not adversely affect other aspects of the system.
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