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參數(shù)資料
| 型號： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
28
Signal Functional Description
(Part 1 of 6)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
HDLCEX Interface
HDLCEXTxClk
Transmit Clock
I
3.3V LVTTL
HDLCEXTxFS
Transmit Frame Synchronization
I
3.3V LVTTL
HDLCEXTxDataA
Transmit Data port A
O
3.3V LVTTL
HDLCEXTxDataB
Transmit Data port B
O
3.3V LVTTL
HDLCEXRxClk
Receive Clock
I
3.3V LVTTL
HDLCEXRxFS
Receive Frame Synchronization
I
3.3V LVTTL
HDLCEXRxDataA
Receive Data port A
I
3.3V LVTTL
HDLCEXRxDataB
Receive Data port B
I
3.3V LVTTL
[HDLCEXTxEnA]
Transmit Enable port A
O
5V tolerant
3.3V LVTTL
[HDLCEXTxEnB]
Transmit Enable port B
O
5V tolerant
3.3V LVTTL
Ethernet Interface
EMC0MDClk
Management Data Clock. The MDClk is sourced to the
PHY. Management information is transferred
synchronously with respect to this clock (MII, RMII, and
SMII).
O
5V tolerant
3.3V LVTTL
EMC0MDIO
Management Data Input/Output is a bidirectional signal
between the Ethernet controller and the PHY. It is used to
transfer control and status information (MII, RMII, and
SMII).
I/O
5V tolerant
3.3V LVTTL
1, 4
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D]
EMC0TxD1[EMC0Tx0D1][EMC0Tx1D]
EMC0TxD2[EMC0Tx1D0]
EMC0TxD3[EMC0Tx1D1]
Transmit Data. A nibble wide data bus towards the net.
The data is synchronous with PHY0TxClk
(MII 0[RMII 0 and 1][SMII 0, 1, 2, and 3]).
O
3.3V LVTTL
EMC0TxEn[EMC0Tx0En][EMC0Sync]
Transmit Enable. This signal is driven by EMAC2 to the
PHY. Data is valid during the active state of this signal.
Deassertion of this signal indicates end of frame
transmission. This signal is synchronous with PHYTxClk
(MII 0[RMII 0]).
or
SMII Sync.
O
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous
with the PHY0TxClk. It informs the PHY that an error was
detected (MII 0).
or
Transmit Enable [RMII 1].
O
5V tolerant
3.3V LVTTL
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