- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370013 > PowerNP NPe405L (IBM Microeletronics) 32-Bit Embedded Processor(32位嵌入式處理器) PDF資料下載
參數(shù)資料
| 型號： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 43/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | POWERNP NPE405L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當(dāng)前第43頁第44頁第45頁第46頁第47頁第48頁
Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
43
SysClk
SysErr
SysReset
TestEn
TmrClk
SDRAM Interface
BA1:0
BankSel3:0
CAS
ClkEn0:1
DQM3:0
DQMCB
ECC7:0
MemAddr12:0
MemClkOut0:1
MemData31:0
RAS
WE
External Slave Peripheral Interface
DMAReq0:3[GPIO9:12]
DMAAck0:3[GPIO13:16]
EOT0:3[TC0:3]
[GPIO24:27]
PerAddr4:31
PerBLast
PerCS0:3
PerData0:15
PerOE
PerPar0:1
PerR/W
PerReady
PerWBE0:1
PerClk
PerErr
PerWE[GPIO31]
n/a
n/a
n/a
dc
n/a
n/a
n/a
n/a
dc
n/a
n/a
5.3
n/a
n/a
async
n/a
1.7
n/a
n/a
async
n/a
12
12
n/a
n/a
n/a
8
8
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
2.0
n/a
n/a
2.0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0.3
n/a
n/a
0.3
n/a
n/a
7.2
5.8
7.0
4.9
5.9
5.9
5.7
7.2
0.4
5.6
7.4
7.1
1.5
1.0
1.4
1.0
1.0
1.0
1.0
1.4
-1.2
1.0
1.6
1.4
19
19
19
40
19
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
12
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
2, 3
3
2, 3
3
3
3
3
2, 3
3, 4
3
2, 3
2, 3
4.8
n/a
0.0
n/a
7.0
7.5
1.1
1.1
n/a
12
n/a
8
PerClk
PerClk
4.3
-0.1
8.5
1.2
12
8
PerClk
n/a
n/a
n/a
4.8
n/a
3.1
n/a
7.5
n/a
n/a
4.0
n/a
n/a
n/a
n/a
1.0
n/a
0.0
n/a
-0.5
n/a
n/a
-0.6
n/a
8.5
7.4
7.2
9.3
7.6
8.3
7.5
n/a
7.5
0.5
n/a
8.3
0.9
1.4
1.3
1.0
1.4
0.9
1.4
n/a
1.3
-0.9
n/a
1.3
17
12
12
17
12
17
12
n/a
12
17
n/a
12
11
8
8
11
8
11
8
n/a
8
11
n/a
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
5
I/O Specifications—200MHz
(Part 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3.
SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PowerNP NPe405 | 32-Bit Embedded Processor(32位嵌入式處理器（應(yīng)用于網(wǎng)絡(luò)方面，提供高性價比）) |
| PowerPC 401GF | 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器) |
| PowerPC 403GA | 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器) |
| PowerPC 403GB | 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器) |
| PowerPC 403GC | 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| POWERPAC-B | 制造商:IAR Systems 功能描述:PowerPac |
| POWERPAC-S | 制造商:IAR Systems 功能描述:PowerPac |
| POWERPAT PLUS | 制造商:Fluke Electronics 功能描述:SOFTWARE PAT |
| POWERPATPLUS | 制造商:Fluke Electronics 功能描述:Fluke Powerpat Plus |
| POWERPLUG15W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:AC/DC POWER SUPPLY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。