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參數(shù)資料
型號： PPC5604BCLL64
廠商： Freescale Semiconductor
文件頁數(shù)： 38/109頁
文件大?。?/td> 0K
描述： MCU 32BIT 512K 64MHZ
標(biāo)準(zhǔn)包裝： 90
系列： MPC56xx Qorivva
核心處理器： e200z0h
芯體尺寸： 32-位
速度： 64MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 79
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 16
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 28x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Package pinouts and signal descriptions
Freescale Semiconductor
34
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
Table 13. Recommended operating conditions (5.0 V)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
V
VDD1
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
VSS_LV3
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_BV4
SR Voltage on VDD_BV pin (regulator supply)
with respect to ground (VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
Relative to VDD VDD0.1 VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference)
pin with respect to ground (VSS
—VSS0.1 VSS+0.1
V
VDD_ADC5
SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
Relative to VDD VDD0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
—VSS0.1
—
V
Relative to VDD
—VDD+0.1
IINJPAD
SR Injected input current on any pin during
overload condition
—
55
mA
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
50
TVDD
SR VDD slope to ensure correct power up6
—
0.25
V/s
TA C-Grade Part
SR Ambient temperature under bias
fCPU 64 MHz
40
85
°C
TJ C-Grade Part
SR Junction temperature under bias
40
110
TA V-Grade Part
SR Ambient temperature under bias
40
105
TJ V-Grade Part
SR Junction temperature under bias
40
130
TA M-Grade Part
SR Ambient temperature under bias
40
125
TJ M-Grade Part
SR Junction temperature under bias
40
150
1 100 nF capacitance needs to be provided between each VDD/VSS pair.
2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6 Guaranteed by device validation
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