參數(shù)資料
型號(hào)： PSB21911
廠商： SIEMENS A G
元件分類： 數(shù)字傳輸電路
英文描述： ISDN Echocancellation Circuit for Terminal Applications IEC-Q TE
中文描述： DATACOM, ISDN ECHO CANCELLER
文件頁數(shù)： 91/164頁
文件大?。?/td> 1401K
代理商： PSB21911
PSB 21911
PSF 21911
S/G Bit and BAC Bit in TE Mode
Semiconductor Group
91
11.97
D-Channel Request by the Terminal
Figure 31
illustrates the request for the HDLC-controller by the terminal. The start state
is BAC = 1 at DIN after TD1 has expired. That causes the S/G bit to be set to the stop
position.
BAC = 1 received on DIN sets the S/G bit on DOUT to the stop position ("1") at the next
IOM-frame. When the terminal requests access to the HDLC-controller in the ELIC it sets
the BAC-bit at DIN of it’s IEC-Q TE to "0". That causes the D-channel data upstream to
be tied to "0" and the S/G-bit to be set to "1". The ELIC receives the zeros and reacts by
assigning the HDLC-controller to this very terminal. This is indicated via the change of C/
I code downstream at the LT side resulting in the S/G bit to be set to "0" (’go’) after delay
TD1 (see below for the explanation of TD1 and TD2).
The IEC-Q TE will continue to send "0" upstream in the D-channel until the actual HDLC
data arrives at DIN.The HDLC-frame itself, marked by the first "0" in the D-channel will
reset the D-channel back to transparent. This allows to have arbitrary delays between
the S/G bit going to "0" and the D-channel being used without the risk of loosing the
HDLC-controller by sending an abort request consisting of all "1".
At the end of the HDLC-frame the BAC bit is reset to "1" again by the layer-2 controller
(e.g. SMARTLINK; ICC). This causes the S/G bit to be set to "1" in the next IOM frame
which stops a possible second HDLC-frame that could not be processed in the ELIC
anymore.
TD1 and TD2
The delays TD1 and TD2 (see
figure
31
) have the following reasons: TD2 is caused by
the 6ms interval in which an EOC message can be transmitted on the Uko interface. As
an EOC-message can start once every 6 ms and will take 6 ms to be transmitted, TD2
will be 12 ms in the worst case.
TD1 is at minimum 7.5 ms depending on the location of the superframe at the time the
HDLC-controller is requested by the terminal. This delay is necessary because instead
of receiving an EOC-message "go" as requested, the terminal could as well receive the
EOC message "stop" because the HDLC-controller was assigned to an other subscriber
just before .
Flags as interframe Fill
The influence to the upstream D-channel can be disabled while the control of the S/G-
bit via EOC-messages and via the BAC bit still is given as described above by setting
SWST:BS to "0", SWST:SGL to "1" and ADF:CBAC to "1". This is usefull when having a
controlling device in the terminal, that is able to send the interframe timefill "flags".
相關(guān)PDF資料
PDF描述
PT3104C 15 WATT 24V TO 5V/12V/15V ISOLATED DC-DC CONVERTER
PT3100-24V 15 WATT 24V TO 5V/12V/15V ISOLATED DC-DC CONVERTER
PT3106C 15 WATT 24V TO 5V/12V/15V ISOLATED DC-DC CONVERTER
PT3402 "2.5V 12A
PT3403 "1.8V 12A
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSB21911F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface
PSB21911NV5.2 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Infineon Technologies AG 功能描述:
PSB2196 制造商:PULSE 制造商全稱:Pulse A Technitrol Company 功能描述:TELECOMMUNICATIONS PRODUCTS
PSB2196H 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?ISDN Subscriber Access Controller for U_PN-Interface Terminals?
PSB2196N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?ISDN Subscriber Access Controller for U_PN-Interface Terminals
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*