參數(shù)資料
型號： PSD501B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入）
文件頁數(shù)： 21/130頁
文件大?。?/td> 704K
代理商： PSD501B1
PSD5XX Famly
6-21
ZPLDBlock
(Cont.)
Port E Macrocell Structure
Figure 9 shows the PE Macrocell block, which consists of 8 identical macrocells. Each
macrocell output can be connected to its own I/O pin on Port E. There are 3 user
programmable global product terms output from the GPLD’s AND ARRAY which are shared
by all the macrocells in Port E:
J
PE.OE
Enable or tri-state Port PE output pins
J
PE.PR
Preset D flip flop in the macrocells
J
PE.RE
Reset/Clear D flip flop in the macrocells
Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip
flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as
the Reset input pin except it is user configurable.
The circuit of a PE Macrocell is shown in Figure 10. There are 4 product terms from the
GPLD’s AND ARRAY as input to the macrocell. Users can select the polarity of the output
and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop
J
Combinatorial Output
Select output from OR gate
J
GPLD Input
Use Port E pin as dedicated input
J
GPLD Output
Use Port E pin as dedicated output
J
GPLD I/O
Use Port E pin as bidirectional pin
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback from the
combinatorial output, to possibly expand the number of product terms available to
another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not connected
to Port E pin, Port E can be configured to perform other user defined I/O functions.
If pins PE0 and PE1 are used as bus control signal inputs (ALE, PSEN/BHE), the
corresponding macrocells' feedbacks are disabled. The bus control signals are
connected to the ZPLD Input Bus.
The two global product terms assigned for asynchronous clear (PE.RE) and preset (PE.PR)
are mainly for proper PE Macrocell initialization.
The macrocell flip-flop can also be cleared during reset by MACRO-RST, if such an option
is chosen. The clock source is always the input clock CLKIN.
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PDF描述
PSD511B1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
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PSD503B1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
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PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD501B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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