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| 型號(hào)： | PSD501B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入） |
| 文件頁(yè)數(shù)： | 5/130頁(yè) |
| 文件大?。?/td> | 704K |
| 代理商： | PSD501B1 |
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PSD5XX Famly
6-5
General
Description
(Cont.)
The PSD5XX includes an 8 level priority encoded Interrupt Controller. The Interrupt
Controller accepts 4 user defined interrupts and 4 Terminal Counts from the Counter/Timer.
Each interrupt can be individually masked and configured to be level or edge sensitive. A 3
bit interrupt vector is generated that can be read by the microcontroller. The serviced
interrupt will be cleared automatically after the microcontroller has read the interrupt vector.
The PSD5XX contains EPROM and scratchpad SRAM. The EPROM densities are 256K,
512K bit and 1M bit and are divided into four blocks. Each block can be located in a
different address location. The access time of the EPROM includes the address latching
and DPLD decoding. The 16 Kbit Standby SRAM may be used as an extension of the
microcontroller SRAM and also to store backup information that is necessary after a system
power down or power failure. Power to the SRAM is supplied by the Vstby pin. Switching
between V
CC
and Vstby occurs automatically when V
CC
power is removed.
A four bit Page Register enables microcontrollers with limited address space easy access
to the I/O Section, EPROM and SRAM . The Page Register outputs are connected to all
ZPLDs and can be used to page external devices as well as the internal PSD5XX functional
units.
A Power Management Unit (PMU) in the PSD5XX enables the user to control the power
consumption on selected functional blocks based on system requirements. For
microcontrollers that do not generate a Chip Select input (CSI) to the peripheral device, the
PMU includes an Automatic Power Down unit (APD) that will turn off the PSD5XX
(into standby or sleep mode) based on inactivity of the ALE. The polarity of ALE inactivity
can be defined by the user. In addition to power down mode, the PSD5XX includes a
SLEEP mode that will reduce the power consumption to 10 μA.
The PSD5XX family is supported by the PSD Development System (PSDsoft, see Figure 2)
which runs under MS-Windows on the PC. Design entry is done using PSDabel which
creates a minimized logic implementation. PSDabel also provides logic simulation of the
ZPLD. The PSD5XX desired configuration is entered using a simple Window based menu.
The PSD Compiler, which consists of a Fitter and Address Translator, generates an object
file from the PSDabel and MCU code files. The object file can be down loaded to a
programmer (MagicPro
, Data I/O or other third party) or to PSDsilos III providing full chip
simulation.
The PSD5XX standard versions include up to 1 Mb of EPROM, 16 Kbit SRAM, Decode PLD
(DPLD), General Purpose PLD (GPLD), Peripheral PLD (PPLD), four 16-bit Counter/Timers,
an 8-level maskable Interrupt Controller and five 8-bit I/O Ports. They are ideal for general
purpose embedded systems applications.
The PSD5XXM mask-programmable versions deliver the lowest cost PSD5XX
solution. See the Masked-PSD Ordering Information chapter in this databook for the
mask-programmable PSD5XXM ordering procedure.
References in this document to PSD5XX versions are generic and include PSD5XX and
PSD5XXM products.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD511B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| PSD502B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| PSD503B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| PSD502B1-12U | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads |
| PSD502B1-12UI | 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD501B1-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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