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| 型號： | PSD501B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入） |
| 文件頁數(shù)： | 89/130頁 |
| 文件大?。?/td> | 704K |
| 代理商： | PSD501B1 |
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PSD5XX Famly
6-89
Load/Store
The Load operation transacts an Image Register (e.g. IMG0) write into its Counter/Timer
Register (e.g. CNTR0), whereas in the Store operation the Counter/Timer Register (e.g.
CNTR0) writes back into the Image Register (e.g. IMG0).
These signals are valid only when a Counter/timer is active. They are rising edge sensitive
and are used to Load a Counter with a required value or to Store the Counter value in the
associated Image Register.
In Waveform, Pulse and WatchDog modes the microcontroller writes into an Image
Register. The respective Counter/Timer uses that value as its initial counting value. The
data transfer operation from an Image Register into its corresponding counter is called
LOAD. In Event Counting and Time Capture modes the Counter/Timer counts event pulses
or timer clock cycles, respectively. An external event or a software command can cause a
data transfer from the counting element into its Image Register. This operation is defined as
STORE.
These operations are triggered by:
J
Software command
J
Terminal count (in Waveform mode only)
J
PPLD macrocell output
J
Input Pin
Refer to Counter/Timer Command Register and Figure 43 for specific details.
Enable/Dsable
These signals are used to enable or disable the counting of the Counter/Timers. These
signals are controlled by:
J
Software command (Bits 2 and 7 of the Command Registers).
J
PPLD macrocell output
J
Input Pin
Event Count Mode:
In Event Count mode the Enable/Disable signal is edge sensitive and is connected to the
event input signal through the PPLD or pin. In Time Capture mode the Enable/Disable
signal can be set by a software command only.
Refer to Counter/Timer Command Register and Figure 43 for specific details.
Counter/Timer Input/Output
Each Counter can use individual control inputs in port E as input Load/Store or
Enable/Disable signals, and Counter/Timer outputs in port A or port B by selecting alternate
and special functions on the pins assigned to them. The outputs are used in waveform and
pulse modes in which the Counters generate output waveforms or pulses. The inputs can
be used in all modes of operation except WatchDog to create the LOAD/STORE and/or
ENABLE/DISABLE control signals. Port E can be configured as outputs for Terminal Count.
Terminal Count is also available as ZPLD inputs (via pin feedback). Refer to Tables 25, 26
and 27 for further details and configuration of these ports.
PPLDMacrocell
The enable/disable or load/store inputs of each Counter/Timer can be selected through a
PPLD macrocell, whose inputs are two product terms PTT0 and PTT1 from the PPLD’s
AND-array. The polarity of the PPLD macrocell output is programmable. The output of the
PPLD macrocell which is the enable/disable and/or Load/Store input to the Counter/Timer
can be in a Combinatorial mode or Register mode. Figure 44 shows the details of the PPLD
macrocell. Refer to the “ZPLD” section for further information on the PPLD.
Counter/Timer
(Cont.)
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| PSD502B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD503B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD501B1-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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