參數(shù)資料
型號(hào)： PSD503B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入）
文件頁數(shù)： 110/130頁
文件大?。?/td> 704K
代理商： PSD503B1
PSD5XX Famly
6-110
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
V
IH
V
IL
V
IH1
V
IL1
V
HYS
Supply Voltage
All Speeds
4.5
5
5.5
V
High Level Input Voltage
4.5 V < V
CC
< 5.5 V
4.5 V < V
CC
< 5.5 V
(Note 1)
2
V
CC
+.5
0.8
V
Low Level Input Voltage
–0.5
V
Reset High Level Input Voltage
.8 V
CC
–0.5
V
CC
+.5
.2 V
CC
–.1
V
Reset Low Level Input Voltage
(Note 1)
V
Reset Pin Hysteresis
0.3
V
V
OL
Output Low Voltage
I
OL
= 20 μA, V
CC
= 4.5 V
0.01
0.1
V
I
OL
= 8 mA, V
CC
= 4.5 V
I
OH
= –20 μA, V
CC
= 4.5 V
0.15
0.45
V
V
OH
Output High Voltage
4.4
4.49
V
I
OH
= –2 mA, V
CC
= 4.5 V
2.4
3.9
V
V
SBY
I
SBY
I
IDLE
V
DF
SRAM Standby Voltage
2.7
V
CC
1
V
SRAM Standby Current
V
CC
= 0 V
V
CC
> V
SBY
Only on V
STBY
0.5
μA
Idle Current (V
STDBY
Pin)
SRAM Data Retention Voltage
–0.1
0.1
μA
2
V
I
SB
Standby Supply
Current
Power Down Mode
CSI >V
CC
–.3 V (Note 2)
40
100
μA
Sleep Mode
CSI >V
CC
–.3 V (Note 3)
V
SS
< V
IN
> V
CC
.45 < V
IN
> V
CC
10
20
μA
I
LI
I
LO
Input Leakage Current
–1
±.1
1
μA
Output Leakage Current
–10
±5
10
μA
ZPLD_TURBO = OFF,
f = 0 MHz (Note 4)
0
See
Figure 49
ZPLD Adder
ZPLD_TURBO = ON,
f = 0 MHz
400
700
μA/PT
CMiser = ON
and Not Selected
0
0
mA
I
CC
(DC)
(Note 4a)
Operating
Supply Current
CMiser = ON and EPROM
Selected (x8 Data Bus)
EPROM Adder
10
15
mA
CMiser = ON and EPROM
Selected (x16 Data Bus)
15
20
mA
CMiser = OFF
15
20
mA
SRAM Not Selected
0
0
mA
CMiser = ON, SRAM
Selected (x8 Data Bus)
SRAM Adder
25
40
mA
CMiser = ON, SRAM
Selected (x16 Data Bus)
30
45
mA
ZPLD_TURBO = OFF
(Note 4)
ZPLD
I
CC
(AC)
(Note 4a)
ZPLD_TURBO = ON
2
mA/MHz
EPROM or SRAM
2
mA/MHz
Counter/Timer
1
mA/MHz
DC Characteristics
(5 V ± 10% Versions)
NOTES:
1.
2.
3.
4.
4.a I
OUT
= 0 mA.
Reset input has hysteresis. V
IL1
is valid at or below .2V
CC
–.1. V
IH1
is valid at or above .8V
CC
.
CSI deselected or internal PD is active.
Sleep mode bit is set and internal PD is active.
See ZPLD ICC/Frequency Power Consumption graph for details.
相關(guān)PDF資料
PDF描述
PSD502B1-12U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads
PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
PSD502B1-15J 600V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package. Also available in Radiation Levels up to 300KRad.; Similar to IRHY67C30CM with Optional Total Dose Rating of 300kRads
PSD502B1-15JI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; Similar to IRHY57Z30CM with optional Total Dose Rating of 300kRads
PSD502B1-15LI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; A IRHY57Z30CM with Standard Packaging
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD503B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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