參數(shù)資料
型號(hào): PSD503B1
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
中文描述: 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備(可編程邏輯,16K的位的SRAM,40余個(gè)可編程輸入/輸出,通用PLD的有61個(gè)輸入)
文件頁數(shù): 78/130頁
文件大小: 704K
代理商: PSD503B1
PSD5XX Famly
6-78
DLCY
Scale Bit
DIV
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DLCY
Scale Bit
DIV
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
40
48
56
64
72
80
88
96
104
112
120
128
136
144
152
160
168
176
184
192
200
208
216
224
232
240
248
256
264
272
280
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 22. DLCY, Scale Bit and DIV to Generate Dfferent Clock Dvisions
Sample Calculation of Timer Input Clock
External input clock to the PSD5XX is 8 MHz.
If required Counter/Timers 0 – 3 count frequency is 1 MHz then
The Counter/Timer CLOCK Input
(External Clock input)
=
(DIV)
8 MHz
(DIV)
1 MHz =
=
>
(DIV) = 8
Therefore from Table 22 when (DIV) = 8, the Scale-Bit in the “Global Command Register” is
set to a 0 and the DLCY register to a value of 4.
Counter/Timer
Operation
(Cont.)
Counter/Timer Clock Input
(Cont.)
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