參數(shù)資料
型號： PSD503B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入）
文件頁數(shù)： 93/130頁
文件大?。?/td> 704K
代理商： PSD503B1
PSD5XX Famly
6-93
Counter/Timer
(Cont.)
Sample Counter/Timer0 Initialization In PULSE Mode
Following is a sample initialization routine for Counter/Timer0 to operate in PULSE mode.
The assembly language commands do not correspond to any particular microcontroller.
Configure CSIOP for Microcontroller access to Counter/Timer registers and I/O ports for
initialization of Counter/Timers. For the values of each register, refer to Tables 30 and 31.
Use PSDsoft supplied by WSI to configure the portion related to Counter/Timers. Also refer
to the Section on the PSD5XX I/O Ports.
Clear All Counter/Timers
LOAD CNTR0, 0000h
LOAD CNTR1, 0000h
LOAD CNTR2, 0000h
LOAD CNTR3, 0000h
; Clear Counter/Timer 0
; Clear Counter/Timer 1
; Clear Counter/Timer 2
; Clear Counter/Timer 3
Scaling of Clock (common to all Counter/Timers)
LOAD DLCY, 02h
;Delay Cycles(DLCY) = 2, k value is selected in
;Global Register by setting Scale-Bit
Counter/Timer 0 Initialization (Command Register0 CMD0)
LOAD CMD0, 6Fh
;Pulse mode (D0 = 1)
;Increment (D1 = 1)
;Select Counter/Timer (D2 = 1)
;Output Pulse Active High (D3 = 1)
;Load Signal on Input pin High going transition (D4 = 0)
;Input control from PIN (not PPLD macrocell) (D5 = 1)
;Load&Store control activated by Pin (D6 = 0)
;Enable count (D7 = 1)
LOAD IMG0,FFF7h
;Load Counter/Timer0 Image Register with count (pulse width)
;needed (pulse duration of 8 timer clock cycles)
LOAD Special Reg A,1
;Configure PA0 as A timer = 0 output by writing a “1” to Port A
;Special Function Register
Gobal Register Configuration
LOAD Global, 03h
;Non WatchDog mode
;Pulse mode
;All CTUs enabled
;Scale-Bit = 1
;Input clock is divided by 6
Now if Pin PE3 on port E is input with a high going signal:
J
This signal causes Counter/Timer0 to get a value (FFF7h) loaded from its
associated image register (IMG0) and causes the Counter/Timer0 to start counting
from FFF7h (increment) until it overflows and issues a Terminal Count0 (TC0).
J
During counting Port A pin (PA0) outputs a high going one-shot pulse with a width
equal to (Max count possible – initial count value loaded, i.e. 8 timer clock cycles
in this example).
J
If the interrupt controller is configured to receive TC0, it will cause the interrupt
INT0 to occur.
相關(guān)PDF資料
PDF描述
PSD502B1-12U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads
PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
PSD502B1-15J 600V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package. Also available in Radiation Levels up to 300KRad.; Similar to IRHY67C30CM with Optional Total Dose Rating of 300kRads
PSD502B1-15JI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; Similar to IRHY57Z30CM with optional Total Dose Rating of 300kRads
PSD502B1-15LI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; A IRHY57Z30CM with Standard Packaging
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD503B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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