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PSD81XFX, PSD83XF2, PSD85XF2
Data Toggle.
Checking the Toggle Flag (DQ6) bit
is a method of determining whether a Program or
Erase cycle is in progress or has completed. Fig-
ure 6 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD8XXFX be-
gins. The MCU then reads the location of the byte
to be programmed in Flash memory to check sta-
tus. The Toggle Flag (DQ6) bit of this location tog-
gles each time the MCU reads this location until
the embedded algorithm is complete. The MCU
continues to read this location, checking the Tog-
gle Flag (DQ6) bit and monitoring the Error Flag
(DQ5) bit. When the Toggle Flag (DQ6) bit stops
toggling (two consecutive reads yield the same
value), and the Error Flag (DQ5) bit remains 0, the
embedded algorithm is complete. If the Error Flag
(DQ5) bit is 1, the MCU should test the Toggle
Flag (DQ6) bit again, since the Toggle Flag (DQ6)
bit may have changed simultaneously with the Er-
ror Flag (DQ5) bit (see Figure 6).
Figure 6. Data Toggle Flowchart
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a 1 to a bit that was not erased
(not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 6 still applies. the Toggle Flag
(DQ6) bit toggles until the Erase cycle is complete.
A 1 on the Error Flag (DQ5) bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er-
ror. The MCU can read any location within the sec-
tor being erased to get the Toggle Flag (DQ6) bit
and the Error Flag (DQ5) bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock Bypass (PSD833F2x, PSD834F2x,
PSD853F2x, PSD854F2x).
The Unlock Bypass
instructions allow the system to program bytes to
the Flash memories faster than using the standard
Program instruction. The Unlock Bypass mode is
entered by first initiating two Unlock cycles. This is
followed by a third WRITE cycle containing the Un-
lock Bypass code, 20h (as shown in Table 8).
The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec-
ond cycle contains the program address and data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset Flash in-
struction. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to READ Mode.
READ
DQ5 & DQ6
START
READ DQ6
FAIL
PASS
AI01370B
D=
TOGGLE
NO
NO
YES
YES
DQ5
= 1
NO
YES
D=
TOGGLE