參數(shù)資料
型號： PSD813F5V
英文描述： -60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA9064 with optional Total Dose Rating of 300kRads
中文描述： Flash在系統(tǒng)編程（ISP）外設(shè)的8位微控制器
文件頁數(shù)： 9/103頁
文件大?。?/td> 1185K
代理商： PSD813F5V
9/103
PSD81XFX, PSD83XF2, PSD85XF2
KEY FEATURES
I
A simple interface to 8-bit microcontrollers that
use either multiplexed or non-multiplexed
busses. The bus interface logic uses the control
signals generated by the microcontroller
automatically when the address is decoded and
a READ or WRITE is performed. A partial list of
the MCU families supported include:
– Intel 8031, 80196, 80186, 80C251, and
80386EX
– Motorola 68HC11, 68HC16, 68HC12, and
683XX
– Philips 8031 and 8051XA
– Zilog Z80 and Z8
I
Internal 1 or 2 Mbit Flash memory. This is the
main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with
user-specified addresses.
I
Internal secondary 256 Kbit Flash boot memory.
It is divided into four equal-sized blocks that can
be accessed with user-specified addresses.
This secondary memory brings the ability to
execute code and update the main Flash
concurrently
.
I
Optional 16, 64 or 256 Kbit SRAM. The SRAM’s
contents can be protected from a power failure
by connecting an external battery.
I
CPLD with 16 Output Micro Cells (OMCs) and
24 Input Micro Cells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.
I
Decode PLD (DPLD) that decodes address for
selection of internal memory blocks.
I
27 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
open-drain outputs.
I
Standby current as low as 50 μA for 5 V devices.
I
Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
I
Internal page register that can be used to
expand the microcontroller address space by a
factor of 256.
I
Internal programmable Power Management
Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the PSD8XXF into Power-down
mode.
I
Erase/WRITE cycles:
– Flash memory – 100,000 minimum
– PLD – 1,000 minimum
– Data Retention: 15 year minimum (for Main
Flash memory, Boot, PLD and Configuration
bits)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813F5VA-15J 功能描述:SPLD - 簡單可編程邏輯器件 3.0V 1M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F5VA-15U 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2VA-15U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813FH-15J 制造商:WSI 功能描述:
PSD813FH-90J 制造商:WSI 功能描述:
PSD813FN-15J 制造商:WSI 功能描述:
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