參數(shù)資料
型號(hào)： PH28F640L18T85
廠商： INTEL CORP
元件分類(lèi)： PROM
英文描述： StrataFlash Wireless Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA56
封裝： 0.75 MM PITCH, LEAD FREE, VFBGA-56
文件頁(yè)數(shù)： 22/106頁(yè)
文件大?。?/td> 1272K
代理商： PH28F640L18T85
Intel StrataFlash Wireless Memory (L18)
April 2005
22
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
WP#
Input
FLASH WRITE PROTECT:
Low-true; WP# enables/disables the lock-down protection mechanism of
the selected flash die. WP#-low enables the lock-down mechanism - locked down blocks cannot be
unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked
down blocks to be unlocked with software commands.
ADV#
Input
FLASH ADDRESS VALID:
Active-low input. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
R-UB#
R-LB#
Input
RAM UPPER / LOWER BYTE ENABLES:
Low-true; During RAM reads, R-UB#-low enables the RAM
high order bytes on DQ[15:8], and R-LB#-low enables the RAM low-order bytes on DQ[7:0].
Treat this signal as NC (No Connect) for this device.
RST#
Input
FLASH RESET:
Low-true; RST#-low initializes flash internal circuitry and disables flash operations.
RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode.
P-Mode
Input
PSRAM MODE:
Low-true; P-MODE is used to program the configuration register, and enter/exit low
power mode.
Treat this signal as NC (No Connect) for this device.
VPP,
VPEN
Power/
Input
Flash Program/Erase Power:
A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
PP
≤
V
PPLK
. Block erase and program at invalid V
PP
voltages should
not be attempted.
Set V
= V
for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the V
level of V
can be as low as V
min. V
must remain above
V
PPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles.
VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VPEN (Erase/Program/Block Lock Enables) is not available for L18 products.
F1-VCC
F2-VCC
Power
Flash Logic Power:
F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power
to the core logic of flash die #2. Write operations are inhibited when V
CC
≤
V
LKO
. Device operations at
invalid V
CC
voltages should not be attempted.
S-VCC
Power
SRAM Power Supply:
Supplies power for SRAM operations.
Treat this signal as NC (No Connect) for this device.
P-VCC
Power
PSRAM Power Supply:
Supplies power for PSRAM operations.
Treat this signal as NC (No Connect) for this device.
VCCQ
Power
Flash I/O Power:
Supply power for the input and output buffers.
VSS
Power
Ground:
Connect to system ground. Do not float any VSS connection.
RFU
—
Reserved for Future Use:
Reserve for future device functionality/ enhancements. Contact Intel
regarding their future use.
DU
—
Do Not Use:
Do not connect to any other signal, or power supply; must be left floating.
NC
—
No Connect:
No internal connection; can be driven or floated.
Table 2.
Device Signal Descriptions for SCSP (Sheet 2 of 2)
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