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| 型號(hào)： | PSOC |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁(yè)數(shù)： | 100/148頁(yè) |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
100
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
The SAR hardware accelerator is a block of specialized
hardware designed to sequence the SAR algorithm for
efficient A/D conversion. A SAR ADC is implemented
conceptually with a DAC of the desired precision, and a
comparator. This functionality can be configured from
one or more PSoC blocks. For each conversion, the firm-
ware should initialize the ASY_CR register as defined
below, and set the sign bit of the DAC as the first guess
in the algorithm. A sequence of OR instructions (Read,
Modify, Write) to the DAC (CR0) register is then exe-
cuted. Each of these OR instructions causes the SAR
hardware to read the current state of the comparator,
checking the validity of the previous guess. It either
clears it or leaves it set, accordingly. The next LSB in the
DAC register is also set as the next guess. Six OR
instructions will complete the conversion of a 6-bit DAC.
The resulting DAC code, which matches the input volt-
age to within 1 LSB, is then read back from the DAC
CR0 register.
10.12.1 Analog Stall and Analog Stall Lockup
Stall lockup affects the operation of stalled IO writes,
such as DAC writes and the stalled IOR of the SAR hard-
ware accelerator. The DAC and SAR User Modules
operate in this mode. The analog column clock fre-
quency must not be a power of two multiple (2, 4, 8...)
higher than the CPU clock frequency. Under this condi-
tion, the CPU will never recover from a stall.
See the list of relationships (in MHz) that will fail:
You can still run the CPU clock slower than the column
clock if the relationship is not a power of two multiple.
For example, you can run at 0.6 MHz, which is not a
power of two multiple of any CPU frequency and there-
fore any CPU frequency can be selected. If the CPU fre-
quency is greater than or equal to the analog column
clock, there is not a problem.
Analog Synchronization Control Register (ASY_CR, Address = Bank 0, 65h)
Table 77:
Analog Frequency Relationships
Analog Column Clock
CPU Clock
3.
1.5, 0.75, .018, 0.093
1.5
0.75, 0.18, 0.093
0.75
0.18, 0.093
0.37
0.18, 0.093
0.18
0.093
Table 78:
Analog Synchronization Control Register
Bit #
POR
Read/
Write
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
--
W
W
W
RW
RW
RW
RW
Bit Name
Reserved
SARCOUNT
[2]
SARCOUNT
[1]
SARCOUNT
[0]
SAR-
SIGN
SARCOL
[1]
SARCOL
[0]
SYN-
CEN
Bit 7
:
Reserved
Bit [6:4]
:
SARCOUNT [2:0]
Initial SAR count. Load this field with the number of bits to process. In a typical 6-bit
SAR, the value would be 6
Bit 3
:
SARSIGN
Adjust the SAR comparator based on the type of block addressed. In a DAC configuration with
more than one PSoC block (more than 6-bits), this bit would be 0 when processing the most significant block and 1
when processing the least significant block. This is because the least significant block of a DAC is an inverting input
to the most significant block
Bit [2:1]
:
SARCOL [1:0]
Column select for SAR comparator input. The DAC portion of the SAR can reside in any of
the appropriate positions in the analog PSOC block array. However, once the comparator block is positioned (and it
is possible to have the DAC and comparator in the same block), this should be the column selected
Bit 0
:
SYNCEN
Set to 1, will stall the CPU until the rising edge of PHI1, if a write to a register within an analog Switch
Cap block takes place
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