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| 型號(hào)： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁(yè)數(shù)： | 75/148頁(yè) |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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Analog PSoC Blocks
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
75
10.7
Analog Clock Select Register
Analog Clock Select Register (CLK_CR1, Address = Bank 1, 61h)
There are a total of twelve analog PSoC blocks imple-
mented for each of the following types; Analog Continu-
ous Time Type A (ACAxx), Analog Switch Cap Type A
(ASAxx), and Analog Switch Cap Type B (ASBxx).
These blocks are arranged in an array of three rows by
four columns. Each column has one of each type of
PSoC block, and the individual PSoC blocks are identi-
fied by the row and column in which they reside.
There are two primary types of analog PSoC blocks.
Both types contain one op-amp but their principles of
operation are quite different. Continuous-time PSoC
blocks employ three configuration registers and use
resistors to condition amplifier response. Switched
capacitor blocks have one comparator and four configu-
ration registers and operate as discrete-time sampling
operators. In both types, the configuration registers are
Table 64:
Analog Clock Select Register
Bit #
POR
Read/
Write
Bit Name
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Reserved
SHDIS
ACLK1 [2]
ACLK1 [1]
ACLK1 [0]
ACLK0 [2]
ACLK0 [1]
ACLK0 [0]
Bit 7
:
Reserved
Bit 6
:
SHDIS
During normal operation of an SC block for the amplifier of a column enabled to drive the output bus,
the connection is only made for the last half of PHI2 (during PHI1 and for the first half of PHI2, the output bus floats
at the last voltage to which it was driven). This forms a sample and hold operation using the output bus and its asso-
ciated capacitance. This design prevents the output bus from being perturbed by the intermediate states of the SC
operation (often a reset state for PHI1 and settling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the out-
put is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Sample and hold function enabled
1 = Sample and hold function disabled
Bit [5:3]
:
ACLK1 [2:0]
0 0 0 = Digital Basic Type A Block 00
0 0 1 = Digital Basic Type A Block 01
0 1 0 = Digital Basic Type A Block 02
0 1 1 = Digital Basic Type A Block 03
1 0 0 = Digital Communications Type A Block 04
1 0 1 = Digital Communications Type A Block 05
1 1 0 = Digital Communications Type A Block 06
1 1 1 = Digital Communications Type A Block 07
Bit [2:0]
:
ACLK0 [2:0]
Same configurations as ACLK1 [2:0]
0 0 0 = Digital Basic Type A Block 00
0 0 1 = Digital Basic Type A Block 01
0 1 0 = Digital Basic Type A Block 02
0 1 1 = Digital Basic Type A Block 03
1 0 0 = Digital Communications Type A Block 04
1 0 1 = Digital Communications Type A Block 05
1 1 0 = Digital Communications Type A Block 06
1 1 1 = Digital Communications Type A Block 07
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