參數(shù)資料
型號(hào): PSOC
廠商: Cypress Semiconductor Corp.
英文描述: 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers
中文描述: 8位可編程系統(tǒng)(的PSoC⑩)微控制器片上
文件頁(yè)數(shù): 8/148頁(yè)
文件大?。?/td> 1412K
代理商: PSOC
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
8
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Table 46: Interrupt Vector Register ............................................................................................................46
Table 47: Digital Basic Type A/ Communications Type A Block xx Function Register...............................50
Table 48: Digital Basic Type A / Communications Type A Block xx Input Register ...................................51
Table 49: Digital Function Data Input Definitions .......................................................................................52
Table 50: Digital Basic Type A / Communications Type A Block xx Output Register.................................53
Table 51: Digital Function Outputs.............................................................................................................54
Table 52: Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2...........................54
Table 53: R/W Variations per User Module Selection ................................................................................55
Table 54: Digital Basic Type A / Communications Type A Block xx Control Register 0.............................55
Table 55: Digital Basic Type A/Communications Type A Block xx Control Register 0...............................56
Table 56: Digital Communications Type A Block xx Control Register 0.....................................................57
Table 57: Digital Communications Type A Block xx Control Register 0.....................................................58
Table 58: Digital Communications Type A Block xx Control Register 0.....................................................59
Table 59: Global Input Assignments...........................................................................................................60
Table 60: Global Output Assignments........................................................................................................60
Table 61: Analog System Clocking Signals................................................................................................72
Table 62: Analog Reference Control Register............................................................................................73
Table 63: Analog Column Clock Select Register........................................................................................74
Table 64: Analog Clock Select Register.....................................................................................................75
Table 65: Analog Continuous Time Block xx Control 0 Register................................................................80
Table 66: Analog Continuous Time Block xx Control 1 Register................................................................81
Table 67: Analog Continuous Time Type A Block xx Control 2 Register ...................................................82
Table 68: Analog Switch Cap Type A Block xx Control 0 Register ............................................................86
Table 69: Analog Switch Cap Type A Block xx Control 1 Register ............................................................88
Table 70: Analog Switch Cap Type A Block xx Control 2 Register ............................................................90
Table 71: Analog Switch Cap Type A Block xx Control 3 Register ............................................................91
Table 72: Analog Switch Cap Type B Block xx Control 0 Register ............................................................93
Table 73: Analog Switch Cap Type B Block xx Control 1 Register ............................................................95
Table 74: Analog Switch Cap Type B Block xx Control 2 Register ............................................................97
Table 75: Analog Switch Cap Type B Block xx Control 3 Register ............................................................98
Table 76: Analog Comparator Control Register .........................................................................................99
Table 77: Analog Frequency Relationships..............................................................................................100
Table 78: Analog Synchronization Control Register.................................................................................100
Table 79: Analog Input Select Register....................................................................................................102
Table 80: Analog Output Buffer Control Register.....................................................................................104
Table 81: Analog Modulator Control Register ..........................................................................................105
Table 82: Multiply Input X Register...........................................................................................................108
Table 83: Multiply Input Y Register...........................................................................................................108
Table 84: Multiply Result High Register ...................................................................................................109
Table 85: Multiply Result Low Register ....................................................................................................109
Table 86: Accumulator Result 1 / Multiply/Accumulator Input X Register ................................................109
Table 87: Accumulator Result 0 / Multiply/Accumulator Input Y Register ................................................109
Table 88: Accumulator Result 3 / Multiply/Accumulator Clear 0 Register ................................................110
Table 89: Accumulator Result 2 / Multiply/Accumulator Clear 1 Register ................................................110
Table 90: Decimator/Incremental Control Register ..................................................................................111
Table 91: Decimator Data High Register..................................................................................................111
Table 92: Decimator Data Low Register...................................................................................................111
Table 93: Processor Status and Control Register....................................................................................112
Table 94: Reset WDT Register.................................................................................................................114
Table 95: Voltage Monitor Control Register .............................................................................................116
Table 96: Bandgap Trim Register.............................................................................................................118
Table 97: CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM) ..........................119
Table 98: Table Read for Supervisory Call Functions..............................................................................120
Table 99: Flash Program Memory Protection...........................................................................................120
相關(guān)PDF資料
PDF描述
PSOT03LC ULTRA LOW CAPACITANCE TVS ARRAY
PS0T03LC ULTRA LOW CAPACITANCE TVS ARRAY
PSOT05LC ULTRA LOW CAPACITANCE TVS ARRAY
PSOT08LC ULTRA LOW CAPACITANCE TVS ARRAY
PSOT12LC D-SUB
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSOK10001 制造商:Value Added 功能描述:
PSOODO3A 制造商:MACOM 制造商全稱(chēng):Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
PSOODO3B 制造商:MACOM 制造商全稱(chēng):Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
PSOODO6A 制造商:MACOM 制造商全稱(chēng):Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
PSOODO6B 制造商:MACOM 制造商全稱(chēng):Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint