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| 型號(hào)： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁(yè)數(shù)： | 122/148頁(yè) |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
122
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
11.10.2.6
Device Checksum (at Low Vcc and High Vcc)
The device checksum is retrieved from the device and
compared to the “Device Checksum” from the user’s file
(Note that this is NOT the same thing as the “Record
Checksum.”) The checksum is retrieved from the device
with the following sequence:
CHECKSUM-SETUP(max_data_block)
WAIT-AND-POLL
READ-CHECKSUM(data)
Note
: This should be done 2 times; once at Vcc=Vcchv
and once at Vcc=Vcclv.
11.10.2.7
Power Down
The last step is to power down the device. This is
accomplished by the following sequence:
Set SDATA=HighZ (float pin P1[0])
Set SCLK=0V (Vin on pin P1[1]=Vilp)
Set Vcc = 0V
11.11 Programming Wave Forms
Notes
:
11.12 Programming File Format
The programming file is created by PSoC Designer, the
Cypress MicroSystems development tool. This tool gen-
erates the programming file in an Intel Hex format.
The programmer should assume the data is 30h/HALT if
it is not specified in the user’s data file.
Figure 33: Programming Wave Forms
Vcc
SDATA
SCLK
OUT
OUT
IN
IN
Tssclk
Thsclk
1
Vcc is only turned off (0V) at the very beginning and the very end of the flow - not within the programming flow.
2
When the programmer puts the driver on SDATA in a High Z (floating) state, the SDATA pin will float to a low
due to an internal device pull down circuit.
3
SCLK is set to VILP during the power up and power down; at other times the SCLK is “free running.” The fre-
quency of the hardware’s SCLK signal must be known by the software because the value (entered in the num-
ber of MegaHertz multiplied by the number 5) must be passed into the device with the SET-CLK-FREQ()
mnemonic.
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