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| 型號： | PXB4340E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 46/66頁 |
| 文件大小： | 869K |
| 代理商： | PXB4340E |
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Data Sheet
6-46
07.2000
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&DVFDGH,QWHUIDFH
For more demanding applications, two CAME chips can be cascaded to build up one virtual
device with double capacity and the identical physical bus interface to an external controller. The
Cascade Interface is used for this purpose and consists of the CO(2..0) outputs and the CI(2..0)
and CA inputs as shown in
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.
)LJXUH
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Both CAME chips receive the same requests from ALP. Depending on the request, the
determination of which chip may answer at the end of the request is either known in advance
(read, write and test requests #4..6) or results from the operation (search requests #1..3). In the
second case, the master must inform the slave of its search result and indicate whether or not it
processes the search request. The same report takes place from the slave to the master. This
is done with the signals CO(1..0). Processing the crosswise transferred status information is
done according to
WDEOH
. The timing of this transfer is defined in
WDEOH
the CO(1..0) signals at this time is done according to
WDEOH
.
In order to avoid bus conflicts on reading of cascaded CAME chips, the master has the
opportunity to disable data output of the slave CAME using the CO(2) signal. This signal is
important in case of a parity error, for example.
The CO(2..0) outputs must be connected to the CI(2..0) inputs of the opposite CAME.
. The interpretation of
1k
CAME
CA
CI(0)
CI(1)
CI(2)
CO(0)
CO(1)
CO(2)
ALP
Bus
interface
CAME
(Master)
CA
CI(2:0)
CO(2:0)
1k
GND
GND
Bus
interface
ALP
CAME
(Slave)
CA
CI(2:0)
CO(2:0)
10k
+ 3.3 V
Bus
interface
a) Single CAME application
a) 2 CAME application
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相關代理商/技術參數(shù) |
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| PXB4340EV1.1-G | 制造商:Infineon Technologies AG 功能描述: |
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