參數(shù)資料
型號(hào)： REFERENCEMANUAL
英文描述： Reference Manual - ElanSC400 Register Set Reference Manual (Including Changes for the 蒷anSC410 Microcontroller)
中文描述： 參考手冊(cè)- ElanSC400寄存器組參考手冊(cè)（包括微控制器的蒷anSC410變化）
文件頁數(shù)： 15/40頁
文件大?。?/td> 405K
代理商： REFERENCEMANUAL
élanSC400 Microcontroller Register Set Reference Manual Amendment
15
A M E N D M E N T
3-106 I/O Access SMI Enable
Register B, Index 9Ah;
descriptions for
bits 6
–0
1 = Cause an SMI due to....
1 = Cause an SMI due to.... Requires
special handling; see Programming
Notes section.
For all seven
bits, add
reference to
programming
notes.
I/O Access SMI Enable
Register B, Index 9Ah;
Programming Notes
Programming Notes
Programming Notes
Special handling for SMI to emulate
I/O accesses:
If the system requires the use of
emulating and/or restarting I/O
accesses, then the software must
select the 80486 cache policy as
write through via CSC index 14h,
bit 0.
Do not
use the I/O Trap
address in SMBASE offset 0FF06h
to determine which I/O address to
emulate. Instead, to determine the
I/O address to emulate, the software
should examine the saved values of
the EIP and CS at SMBASE offsets
0FFF0h and 0FFACh, respectively.
The software then examines the
instruction that caused the SMI by
decrementing the EIP value,
determining the opcode, and using
the DX and AX registers in the SMM
save state or opcode operands to
determine the correct I/O address.
The I/O restart (writing 0FFh to
SMBASE offset 0FF00h) will work
correctly with the write through
policy.
The élanSC400
microcontroller
only supports
I/O trapping with
the write through
cache policy and
requires special
handling.
3-109 XMI Control Register,
Index 9Dh; diagram,
bits 7–3 and bit 2
functions
Reserved
NMI_GATE
Reserved
Add bit 2 to
Reserved field
bits 7–3. Delete
bit 2 description.
The NMI_GATE
function is
performed by
direct-mapped
Port 70h[7] in
the élanSC400
and élanSC410
microcontrollers.
XMI Control Register,
Index 9Dh; bits 7–3
description
7–3 Reserved...
7–2 Reserved...
XMI Control Register,
Index 9Dh; bit 2
description
2 NMI_GATE
Master NMI Enable
...
(entire description)
3-116 GPIO Read-Back/Write
Register A–D, Index
A6h, A7h, A8h, A9h;
default bit values in
diagram
x x x x x x x x
“” = depends
on input state.
3-122 GPIO_PMUB Mode
Change Register,
Index ABh; bit 4
description
Drive GPIO_PMUB Signal with
Programmed Value in Hyper-
Speed Mode
Drive GPIO_PMUB Signal with
Programmed Value in High-Speed
Mode
Correction.
Table 1.
Corrections to the
élanSC400 Microcontroller Register Set Reference Manual
(Continued)
Page Item
Original Text
Change To
Comment
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