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élanSC400 Microcontroller Register Set Reference Manual Amendment
37
A M E N D M E N T
Graphics Index 3Eh, 30
Graphics Index 3Fh, 30
Graphics Index 40h, 30
Graphics Index 41h, 30
Graphics Index 42h, 30
Graphics Index 43h, 30
Graphics Index 44–4Bh, 30
Graphics Index 4Ch, 22, 30
Graphics Index 4Dh, 30
Graphics Index 4Eh, 30
Graphics Index 4Fh, 30
Graphics Index 50h, 30
Graphics Index 51h, 30
Graphics Index 52h, 30
H
HGA Configuration Register, 27
Horizontal Border End Register, 29
Horizontal Display End Register, 29
Horizontal Line Pulse Start Register, 29
Horizontal Total Register, 29
I
I/O Access SMI Enable Register A, 14, 28
I/O Access SMI Enable Register B, 15, 28
I/O Access SMI Status Register A, 28
I/O Access SMI Status Register B, 28
I/O Window 0 Start Address High Register, 31
I/O Window 0 Start Address Low Register, 31
I/O Window 0 Stop Address High Register, 31
I/O Window 0 Stop Address Low Register, 31
I/O Window 1 Start Address High Register, 31
I/O Window 1 Start Address Low Register, 31
I/O Window 1 Stop Address High Register, 31
I/O Window 1 Stop Address Low Register, 31
I/O Window Control Register, 31
Identification and Revision Register, 30
Interface Status Register, 23, 30
Internal Graphics Control Register A, 28
Internal Graphics Control Register B, 28
Internal I/O Device Disable/Echo Z-Bus Configuration
Register, 28
Internal I/O Device Disable/Internal Cycle Echo Config-
uration Register, 16
Interrupt and General Control Register, 23, 31
Interrupt Configuration Register E, 17
IrDA Control Register, 18
IrDA CRC Status Register, 18
IrDA Frame Length Register A, 19
IrDA Frame Length Register B, 20
K
Keyboard Configuration Register A, 16
Keyboard Configuration Register B, 16
L
LCD Graphics Controller.
See
Graphics Controller
LCD Panel AC Modulation Clock Register, 30
Light Pen High Register, 29
Light Pen Low Register, 29
Linear ROMCS0/Shadow Register, 7, 27
M
Master DMA Clear Byte Pointer Register, 2
Master DMA Controller Reset Register, 3
Master DMA Controller Temporary Register, 3
Master DMA Mask Register Channels 4–7, 2
Master DMA Mode Register Channels 4–7, 2
Master DMA Reset Mask Register, 3
Master Software DRQ(n) Request Register, 2
Maximum Scan Line Register, 30
MDA/HGA Data Register, 27
MDA/HGA Index Register, 27
MDA/HGA Mode Control Register, 27
MDA/HGA Status Register, 27
Memory Window 0 Address Offset High Register, 31
Memory Window 0 Address Offset Low Register, 31
Memory Window 0 Start Address High Register, 31
Memory Window 0 Start Address Low Register, 31
Memory Window 0 Stop Address High Register, 31
Memory Window 0 Stop Address Low Register, 31
Memory Window 1 Address Offset High Register, 32
Memory Window 1 Address Offset Low Register, 32
Memory Window 1 Start Address High Register, 31
Memory Window 1 Start Address Low Register, 31
Memory Window 1 Stop Address High Register, 31
Memory Window 1 Stop Address Low Register, 31
Memory Window 2 Address Offset High Register, 32
Memory Window 2 Address Offset Low Register, 32
Memory Window 2 Start Address High Register, 32
Memory Window 2 Start Address Low Register, 32
Memory Window 2 Stop Address High Register, 32
Memory Window 2 Stop Address Low Register, 32
Memory Window 3 Address Offset High Register, 32
Memory Window 3 Address Offset Low Register, 32
Memory Window 3 Start Address High Register, 32
Memory Window 3 Start Address Low Register, 32
Memory Window 3 Stop Address High Register, 32
Memory Window 3 Stop Address Low Register, 32
Memory Window 4 Address Offset High Register, 32
Memory Window 4 Address Offset Low Register, 32
Memory Window 4 Start Address High Register, 32
Memory Window 4 Start Address Low Register, 32
Memory Window 4 Stop Address High Register, 32
Memory Window 4 Stop Address Low Register, 32
Miscellaneous SMI/NMI Enable Register, 12, 13
MMS Window C–F Attributes Register, 27
MMS Window C–F Device Select Register, 27
MMS Window C–F setup, 27, 28, 29