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參數(shù)資料
| 型號(hào)： | RG82845MP |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 129/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82845MP |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
73
R
3.7.27.
AGPCMD – AGP Command Register – Device #0
Address Offset:
A8-ABh
Default Value:
0000_0000h
Access:
Read/Write, Read Only
Size:
32 bits
This register provides control of the AGP operational parameters.
Bit
Description
31:10
Reserved
9
SBA Enable (SBAEN): When this bit is set to 1, the side band addressing mechanism is enabled.
8
AGP Enable (AGPEN): When this bit is reset to 0, the MCH-M will ignore all AGP operations,
including the sync cycle. Any AGP operations received while this bit is set to 1 will be serviced even if
this bit is subsequently reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of
an SBA command being delivered in 1X mode the command will be issued.
0 = MCH-M will ignore all AGP operations, including the sideband strobe sync cycle.
1 = MCH-M will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if
the AGP Side Band Enable bit is also set to 1.
7:5
Reserved
4
FW Enable (FWEN): When this bit is set, the MCH-M will use the Fast Write protocol for Memory
Write transactions from the MCH-M to the AGP master. Fast Writes will occur at the data transfer
rate selected by the data rate bits (2:0) in this register. When this bit is cleared, or when the data rate
bits are set to 1x mode, the Memory Write transactions from the MCH-M to the AGP master use
standard PCI protocol.
3
Reserved
2:0
Data Rate (DRATE): The settings of these bits determine the AGP data transfer rate. One (and only
one) bit in this field must be set to indicate the desired data transfer rate.
Encoding
Description
0 0 1
1x transfer mode
0 1 0
2x transfer mode
1 0 0
4x transfer mode
Configuration software will update this field by setting only one bit that corresponds to the capability of
AGP master (after that capability has been verified by accessing the same functional register within
the AGP masters’ configuration space.)
NOTE: This field applies to G_AD and SBA buses. It also applies to Fast Writes if they are enabled.
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