參數(shù)資料
型號(hào)： RH80532GC033512
元件分類： 微處理器
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 37/93頁
文件大?。?/td> 2353K
代理商： RH80532GC033512
Mobile Intel
Pentium
4 Processor-M
250686-002
Datasheet
37
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All
Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced o the BCLK0 rising edge
at 0.5*VCC.
3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion and before the deassertion of PROCHOT# for the processor to complete current instruction
execution.
6. See
Section 7.1
for additional timing requirements for entering and leaving the low power states.
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
Table 21. Miscellaneous Signals AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3,6
T35: Asynch GTL+ Input Pulse Width
2
BCLKs
T36: PWRGOOD to RESET# Deassertion
Time
1
10
ms
16
T37: PWRGOOD Inactive Pulse Width
10
BCLKs
16
4
T38: PROCHOT# Pulse Width
500
μ
s
18
5
T39: THERMTRIP# to Vcc Removal
0.5
s
19
T40: FERR# Valid Delay from STPCLK#
Deassertion
0
5
BCLKs
20
Table 22. System Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Setup Time
4
BCLKs
13
1
T46: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Hold Time
2
20
BCLKs
13
2
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