參數(shù)資料
型號： RH80532GC033512
元件分類： 微處理器
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 92/93頁
文件大小： 2353K
代理商： RH80532GC033512
Mobile Intel
Pentium
4 Processor-M
92
Datasheet
250686-002
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the system bus while the
processor is in Deep Sleep state. Any transition on an input signal before the processor has returned
to Stop-Grant state will result in unpredictable behaviour.
7.2.7
Deeper Sleep State
The Deeper Sleep State is the lowest state power the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer
the
Mobile Intel
Pentium
4 Processor-M and Intel
845MP/845MZ Chipset Platform Design
Guide
and
RS-Intel Mobile Voltage Positioning (IMVP)-III Mobile Processor Core Voltage
Regulator Specification Design Guide
for details.
7.3
Enhanced Intel SpeedStep
Technology
The Mobile Intel Pentium 4 Processor-M, when used in conjunction with the requisite Intel
SpeedStep
technology applet or its equivalent, supports Enhanced Intel
SpeedStep
technology.
Enhanced Intel SpeedStep technology allows the processor to switch between two core frequencies
automatically based on CPU demand, without having to reset the processor or change the system
bus frequency. The processor has two bus ratios and voltages programmed into it instead of one
and the GHI# signal controls which bus ratio and volatage is used. After reset, the processor will
start in the lower of its two core frequencies, the “Battery Optimized” mode. An operating mode
transition to the high core frequency can be made by setting GHI# low, putting the processor into
the Deep Sleep state, regulating to the new VID output, and returning to the Normal state. This puts
the processor into the high core frequency, or “Maximum Performance” operating mode. Going
through these steps with GHI# set high transitions the processor back to the low core frequency
operating mode. The processor will drive the VID[4:0] pins with the VID of the current operating
mode and the system logic is required to regulate the core voltage within specification for the
driven VID.
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