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| 型號(hào)： | RH80532GC033512 |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 49/93頁(yè) |
| 文件大小： | 2353K |
| 代理商： | RH80532GC033512 |
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Mobile Intel
Pentium
4 Processor-M
250686-002
Datasheet
49
3.
System Bus Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI)
effects. For these reasons, it is important that the designer work to achieve a solution that provides
acceptable signal quality across all systematic variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and for interpreting results for signal quality measurements of actual designs.
The Mobile Intel Pentium 4 Processor-M
IBIS models should be used while performing signal
integrity simulations.
3.1
System Bus Clock (BCLK) Signal Quality Specifications
and Measurement Guidelines
Table 26
describes the signal quality specifications at the processor pads for the processor system
bus clock (BCLK) signals.
Figure 25
describes the signal quality waveform for the system bus
clock at the processor pads.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M
frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This
specification is an absolute value.
Table 26. BCLK Signal Quality Specifications
Parameter
Min
Max
Unit
Figure
Notes
1
BCLK[1:0] Overshoot
N/A
0.30
V
25
BCLK[1:0] Undershoot
N/A
0.30
V
25
BCLK[1:0] Ringback Margin
0.20
N/A
V
25
2
BCLK[1:0] Threshold Region
N/A
0.10
V
25
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相關(guān)代理商/技術(shù)參數(shù) |
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