參數(shù)資料
型號： RK80530KZ006512
英文描述： MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷
文件頁數(shù)： 32/86頁
文件大?。?/td> 882K
代理商： RK80530KZ006512
32
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies.
2. All timings for the AGTL signals are referenced at the rising edge of BCLK and the falling edge of BCLK# at
the processor pin. All AGTL signal timings (address bus, data bus, etc.) are referenced at 1.00V at the
processor pins.
3. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, 133 MHz.
Table 16
shows the supported ratios for each processor.
4. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured at adjacent crossing points of BCLK and BCLK# which is defined as the rising edge of BCLK and
the falling edge of BCLK# at the processor pin. The jitter present must be accounted for as a component of
BCLK timing skew between devices.
5. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than
500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
6. Measurement taken from differential waveform, defined as BCLK - BCLK#.
7. Rise time is measured from -0.35 to +0.35V and fall time is measured from 0.35V to -0.35V.
8. Measured at the socket pin.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
Cache at all frequencies.
2. These specifications are tested during manufacturing.
3. All timings for the AGTL signals are referenced to the rising edge of BCLK and the falling edge of BCLK# at
the processor pin. All AGTL signal timings (compatibility signals, etc.) are referenced at 0.80V at the
processor pins.
Table 15. System Bus Timing Specifications (Differential Clock)
1, 2, 6
133 MHz
100 MHz
T# Parameter
Min
Max
Min
Max
Unit
Figure
Notes
T1: BCLK Period - average
7.5
7.7
10.0
10.2
nS
9
3, 4
T1
: BCLK Period - Instantaneous
minimum
7.30
9.8
nS
3, 4
T2: BCLK Period Stability
200
200
pS
5
Vcross: Crossing point at 1V Swing
0.51
0.76
0.51
0.76
V
9
T5: BCLK Rise Time
175
550
175
550
pS
10
7, 8
T6: BCLK Fall Time
175
550
175
550
pS
10
7, 8
Rise/Fall Time Matching
325
325
pS
BCLK Duty Cycle
45%
55%
45%
55%
4
Input High Voltage
0.92
1.45
0.92
1.45
V
Input Low Voltage
-0.2
0.35
-0.2
0.35
V
Rising Edge Ring Back
0.35
0.35
V
Falling Edge Ring Back
-0.35
-0.35
V
Table 16. System Bus Timing Specifications (AGTL Signal Group)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL Output Valid Delay
0.40
3.25
ns
11
4
T8: AGTL Input Setup Time
0.95
ns
12
5, 6, 7, 10
T9: AGTL Input Hold Time
1.00
ns
12
8
T10: RESET# Pulse Width
1.00
ms
13
6, 9
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RK80530KZ012512 制造商:Intel 功能描述:MPU Pentium 制造商:Rochester Electronics LLC 功能描述:P3 (TUALATIN) 1.26GHZ 512 CACHE (FOR SERVERS) 133 FSB; 1.45V - Bulk
RK80530KZ012512S L5QL 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA2
RK80530KZ012512S L6BX 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA 制造商:Intel 功能描述:MPU PENTIUM III 64BIT 0.13UM 1.266GHZ 370PIN FCPGA2 - Trays
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RK80530KZ017512S L5XL 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G
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