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參數(shù)資料
| 型號(hào)： | RK80530KZ006512 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁(yè)數(shù)： | 33/86頁(yè) |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ006512 |
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Datasheet
33
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
4. Valid delay timings for these signals are specified into 50
to 1.25V, V
REF
at 0.8 V ±2% and with 56
or
68
on-die R
.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from V
REF
- 200 mV to V
REF
+ 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 0.8 V swing from V
TT
- 0.8V to V
TT
. This assumes an edge rate of 3V/ns.
9. This should be measured after V
CC
, V
TT
, Vcc
, and BCLK (and BCLK#) are stable
10.BREQ signals observe a 1.2nS minimum setup time.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 system bus clocks.
5. When driven inactive or after V
CC
CORE
, V
TT
, V
CCCMOS
, and BCLK and BCLK# are stable.
Table 17. System Bus Timing Specifications (CMOS Signal Group)
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
11
Active and
Inactive states
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
15
5
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| RK80530KZ017512 | 制造商:Rochester Electronics LLC 功能描述:P3 (TUALATIN) 1.4HZ 512 CACHE (FOR SERVERS) 133 FSB; 1.45V - Bulk |
| RK80530KZ017512S L5XL | 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G |
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