- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373275 > RK80530KZ012512 Metal Film Resistor - RN 1/4 T1 110 1% A PDF資料下載
參數(shù)資料
| 型號： | RK80530KZ012512 |
| 英文描述： | Metal Film Resistor - RN 1/4 T1 110 1% A |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 15/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ012512 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
Datasheet
15
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input (see
Section 2.2.6
). Once in the Sleep state, the SLP# pin can be
deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum
assertion of one BCLK period.
2.2.6
Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK is
stopped. BCLK and BCLK# have to be separated by at least 0.2V during the Deep Sleep State.
Stopping of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
NOTES:
1. The values in this table are based on differential probe measurement of the Bclk.
2. The DC voltage level specified must be maintained when the system bus clock is not active, e.g. Deep Sleep
Mode. V
BCLK#
has to be 200 mV less than V
BCLK.
2.2.7
Clock Control
BCLK provides the clock signal for the processor and on-die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor will process a system bus snoop. The processor does not
stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache is
restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor
has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
Table 2.
System Bus Clock in Deep Sleep Mode (Differential Mode only)
1
Symbol
Parameter
Min
Max
Units
Notes
V
BCLK
BCLK Voltage Level when not active
0.4
1.45
V
2
V
BCLK-
V
BCLK#
BCLK# Voltage Level when not active
0
V
BCLK -
0.2
V
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RK80530KZ017512 | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| RK80532PC041512 | Microprocessor |
| RK9410 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 7A I(D) | SO |
| RKC-SERIES | Interface IC |
| RKCB-SERIES | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RK80530KZ012512S L5QL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA2 |
| RK80530KZ012512S L6BX | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA 制造商:Intel 功能描述:MPU PENTIUM III 64BIT 0.13UM 1.266GHZ 370PIN FCPGA2 - Trays |
| RK80530KZ017512 | 制造商:Rochester Electronics LLC 功能描述:P3 (TUALATIN) 1.4HZ 512 CACHE (FOR SERVERS) 133 FSB; 1.45V - Bulk |
| RK80530KZ017512S L5XL | 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G |
| RK80530KZ017512S L6BY | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.4GHz 370-Pin FCPGA2 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。