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參數(shù)資料
| 型號(hào)： | RK80530KZ012512 |
| 英文描述： | Metal Film Resistor - RN 1/4 T1 110 1% A |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 80/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ012512 |
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80
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
FLUSH#
I
When the FLUSH# input signal is asserted, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal
remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH#
to determine its power-on configuration. See the
P6 Family of Processors
Hardware Developer’s Manual
for details.
This signal must be connected to a 150ohm
resistor to V
CCCMOS1.5
. Refer to the
platform design guide for implementation detail and resistor tolerance.
HIT#
HITM#
I/O
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
IERR#
O
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor system bus. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The
processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or
INIT#.
IGNNE#
I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
INIT#
I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to handle
snoop requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
KEY
I
Can be used to prevent legacy processors from booting in incompatible platforms.
Legacy processors use this pin as a RESET and should be tied to ground for an
Intel Pentium III processor with 512KB L2 Cache only platform, but for flexible
platform implementations this pin should be a No Connect. Please refer to the
appropriate Platform Design Guide for implementation details.
LINT[1:0]
I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of
all APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Intel
Pentium
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
Table 39. Signal Description (Sheet 5 of 9)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RK80530KZ017512 | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| RK80532PC041512 | Microprocessor |
| RK9410 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 7A I(D) | SO |
| RKC-SERIES | Interface IC |
| RKCB-SERIES | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RK80530KZ012512S L5QL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA2 |
| RK80530KZ012512S L6BX | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA 制造商:Intel 功能描述:MPU PENTIUM III 64BIT 0.13UM 1.266GHZ 370PIN FCPGA2 - Trays |
| RK80530KZ017512 | 制造商:Rochester Electronics LLC 功能描述:P3 (TUALATIN) 1.4HZ 512 CACHE (FOR SERVERS) 133 FSB; 1.45V - Bulk |
| RK80530KZ017512S L5XL | 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G |
| RK80530KZ017512S L6BY | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.4GHz 370-Pin FCPGA2 |
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