參數(shù)資料
型號(hào)： RK80530KZ012512
英文描述： Metal Film Resistor - RN 1/4 T1 110 1% A
中文描述： 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷
文件頁(yè)數(shù)： 81/86頁(yè)
文件大?。?/td> 882K
代理商： RK80530KZ012512
Datasheet
81
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
LOCK#
I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of
the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
NCHCTRL
I
T
he NCHCTRL input signal provides AGTL pull-down strength control. The Intel
Pentium III processor with 512KB L2 Cache samples this input to determine the
N-channel device strength for pull-down when it is the driving agent. This signal
must be connected to a 14ohm
resistor to V
. Refer to the platform design guide
for implementation detail and resistor tolerance.
PICCLK
I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICD[1:0]
I/O
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.
PLL1, PLL2
I
All Intel Pentium III processors have an internal analog PLL clock generator that
requires a quiet power supply. PLL1 and PLL2 are inputs to this PLL and must be
connected to V
CC
through a low pass filter that minimizes jitter. See the
platform design guide for implementation details.
PRDY#
O
The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PREQ#
I
The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
PWRGOOD
I
The PWRGOOD (Power Good) signal is processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (V
CC
,
etc.) are stable and within their specifications. Clean implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time that
the power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width
specification in
Table 17
, and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]#
I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
Table 39. Signal Description (Sheet 6 of 9)
Name
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RK80530KZ012512S L5QL 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA2
RK80530KZ012512S L6BX 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA 制造商:Intel 功能描述:MPU PENTIUM III 64BIT 0.13UM 1.266GHZ 370PIN FCPGA2 - Trays
RK80530KZ017512 制造商:Rochester Electronics LLC 功能描述:P3 (TUALATIN) 1.4HZ 512 CACHE (FOR SERVERS) 133 FSB; 1.45V - Bulk
RK80530KZ017512S L5XL 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G
RK80530KZ017512S L6BY 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.4GHz 370-Pin FCPGA2
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