參數(shù)資料
型號(hào): RTL8139L
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述: 瑞昱3.3V的單芯片快速以太網(wǎng)控制器電源管理
文件頁(yè)數(shù): 22/62頁(yè)
文件大?。?/td> 648K
代理商: RTL8139L
RTL8139C(L)
2002/01/10
Rev.1.4
22
6.12 Media Status Register
(Offset 0058h, R/W)
This register allows configuration of a variety of device and PHY options, and provides PHY status information.
Bit
7
R/W
R/W
Symbol
TXFCE/
LdTXFCE
Description
Tx Flow Control Enable:
The flow control is valid in full-duplex
mode only. This register’s default value comes from 93C46 (93C56).
RTL8139C(L)
ANE = 1
ANE = 1
ANE = 1
ANE = 0 &
full-duplex mode
ANE = 0 &
half-duplex mode
Remote
TXFCE/LdTXFCE
R/O
R/W
R/W
R/W
NWAY FLY mode
NWAY mode only
No NWAY
-
-
invalid
NWAY FLY mode: NWAY with flow control capability
NWAY mode only: NWAY without flow control capability
RX Flow control Enable:
The flow control is enabled in full-duplex
mode only. The default value comes from 93C46 (93C56).
Reserved
Aux. Power present Status:
1: The Aux. Power is present.
0: The Aux. Power is absent.
The value of this bit is fixed after each PCI reset.
Speed:
Set, when current media is 10 Mbps mode. Reset, when current
media is 100 Mbps mode.
Inverse of Link status:
0 = Link OK. 1 = Link Fail.
Transmit Pause Flag:
Set when the RTL8139C(L) sends pause packet.
Reset when the RTL8139C(L) sends timer done packet.
Receive Pause Flag:
Set when the RTL8139C(L) is in backoff state
because a pause packet received. Reset when pause state is clear.
6
R/W
RXFCE
5
4
-
R
-
Aux_Status
3
R
SPEED_10
2
1
R
R
LINKB
TXPF
0
R
RXPF
6.13 CONFIG 3: Configuration Register3
(Offset 0059h, R/W)
Bit
R/W
Symbol
7
R
GNTSel
Description
Gnt Select:
Select the Frame’s asserted time after the Grant signal has
been asserted. The Frame and Grant are the PCI signals.
1: Delay one clock from GNT assertion
0: No delay
Parameter Enable:
(These parameters are used in 100Mbps mode)
Setting to 0 and 9346CR register EEM1=EEM0=1 enable the
PHY1_PARM, PHY2_PARM, TW_PARM be written via software.
Setting to 1 will allow parameters auto-loaded from 93C46 (93C56)
and disable writing to PHY1_PARM, PHY2_PARM and TW_PARM
registers via software. The PHY1_PARM, PHY2_PARM, and
TW_PARM can be auto-loaded from EEPROM in this mode. The
parameter auto-load process is executed every time when the Link is
OK in 100Mbps mode.
6
R/W
PARM_En
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