參數(shù)資料
型號： RTL8139L
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱3.3V的單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 7/62頁
文件大?。?/td> 648K
代理商： RTL8139L
RTL8139C(L)
2002/01/10
Rev.1.4
7
DEVSELB
S/T/S
19
Device Select:
As a bus master, the RTL8139C(L) samples this signal
to insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8139C(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
Cycle Frame:
As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of a
bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data phase.
FRAMEB
S/T/S
15
As a target, the device monitors this signal before decoding the address
to check if the current transaction is addressed to it.
Grant:
This signal is asserted low to indicate to the RTL8139C(L) that
the central arbiter has granted ownership of the bus to the
RTL8139C(L). This input is used when the RTL8139C(L) is acting as a
bus master.
Request:
The RTL8139C(L) will assert this signal low to request the
ownership of the bus from the central arbiter.
Initialization Device Select
: This pin allows the RTL8139C(L) to
identify when configuration read/write transactions are intended for it.
Interrupt A:
Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask and Interrupt Enable registers.
Initiator Ready
: This indicates the initiating agent’s ability to complete
the current data phase of the transaction.
As a bus master, this signal will be asserted low when the
RTL8139C(L) is ready to complete the current data phase transaction.
This signal is used in conjunction with the TRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB and
TRDYB are asserted low. As a target, this signal indicates that the
master has put data on the bus.
Target Ready:
This indicates the target agent’s ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data
during write operations and with the data during read operations. As a
target, this signal will be asserted low when the (slave) device is ready
to complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low.
Parity:
This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read data phases.
GNTB
I
117
REQB
T/S
118
IDSEL
I
3
INTAB
O/D
114
IRDYB
S/T/S
16
TRDYB
S/T/S
17
PAR
T/S
23
相關(guān)PDF資料
PDF描述
RTL8139 REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139A REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139B REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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