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參數(shù)資料
| 型號： | RTL8305SB |
| 英文描述： | RTL8305SB |
| 中文描述： | RTL8305SB |
| 文件頁數(shù)： | 36/66頁 |
| 文件大?。?/td> | 963K |
| 代理商： | RTL8305SB |
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RTL8305SB
2002/04/09
36
Rev.1.0
MAC mode MII:
In HomePNA or other PHY applications, the RTL8305SB provides the MII interface to the underlying
HomePNA or other physical devices so as to communicate with other types of LAN media. In such applications, the
P4MODE[1:0] pins are floating upon reset and the RTL8305SB supports the UTP/MII auto-detection function. When both
UTP and MII are active (link on), the UTP port has a higher priority over MII port.
In HomePNA applications, P4SPDSTA must be pulled down since HomePNA is half-duplex only. P4DUPSTA should be
pulled down as well. P4LNKSTA# must be pulled down instead of being wired to the LINK LED pin of the HomePNA
because of the unstable link state of HomePNA, a characteristic based on the HomePNA 1.0 standard. Because the HomePNA
PHY physical layer is half duplex and can only detect the collision event during AID header interval (the time for transmit
Ethernet preamble), the back pressure flow control algorithm is not suitable for the HomePNA network. So the P4FLCTRL
pin should be pulled down.
For other PHY applications, P4SPDSTA, P4DUPSTA, and P4FLCTRL depend on application.
7.1.3 Port Status Configuration
The RTL8305SB supports flexible port status configuration for PHY by pin (GxANeg/GyANeg/P4ANeg,
GxSpd100/GySpd100/P4Spd100, and GxFull/GyFull/P4Full) on a group basis upon reset or by internal registers (Reg0.12,
Reg0.13, Reg0.8, and Reg4.5/4.6/4.7/4.8) via SMI on a per port basis after reset. Those pins are used to assign the initial value
of MII register 0 and 4 (PHY registers) upon reset. The registers can be updated via SMI on a per port basis after reset. For
example, the initial value of register 0.12 of port4 will be 0 when pin P4Aneg is 1 upon reset.
Note: The RTL8305S only
supports UTP with Auto-Negotiation ability. Only one pin, NWAYHalf#, is supported for global configuration of all PHYs. And
does not support these registers for configuration via SMI.
All ports support 100Base-FX, which share pins with UTP (TX+-/RX+-) and need no SD+- pins (Realtek patent). The
100Base-FX can be forced into half or full duplex mode with optional flow control ability. In order to operate correctly, both sides
of the connection should set the same duplex and flow control ability. In 100Base-FX, only duplex and flow control ability can be
set via strapped pins upon reset or via SMI after reset. Note that 100Base-FX does not support Auto-Negotiation according to
IEEE 802.3u. Pins GxANeg/GyANeg/P4Aneg as well as GxSpd100/GySpd100/P4Spd100 are not used for 100Base-FX mode
and can be left floating while in 100Base-FX mode. For example: port4 will be forced into full duplex 100Base-FX with flow
control ability when P4Mode[1:0]=10, P4Full=1, P4EnFC=1 upon reset (regardless of P4Spd100 and P4ANeg).
When Auto-Negotiation ability is enabled in UTP mode, the RTL8305SB supports Auto-Negotiation and parallel detection for
10Base-T/100Base-TX to automatically determine line speed, duplex and flow control ability. The parallel detection process is
used when the other side does not support auto-negotiation. For example: port0 is UTP with all abilities (default for normal
switch application: GxMode=1, GxANeg=1, GxSpd100=1, GxFull=1, GxEnFC=1. The content of MII registers will be
Reg0.12=1, Reg4.5=1, Reg4.6=1, Reg4.7=1, Reg4.8=1, and Reg4.10=1.) If the other side is auto-negotiation, 10Full with
802.3x flow control ability, port0 will enter the auto-negotiation process. The result should be 10Full with 802.3x flow control
ability for both sides. If the other side is 10M without auto-negotiation, port0 will enter the parallel detection process. The
result should be 10Half without 802.3x flow control ability for port0.
Note: Each port can operate at 10Mbps or 100Mbps with full-duplex or half-duplex mode independently to others when
auto-negotiation process is on.
The port status for the PHY on a group basis can easily be set by pin configuration. For example, when group X is 100FX
(GxMode=0), group X can be set as force mode half duplex by setting pin GxFull to 0. Group Y can also be set as UTP mode
NWAY mode 10Full by setting pins GyMode=1, GyANeg=1, GySpd100=0, GyFull=1. Refer to the pin descriptions for details.
7.1.4 Enable Port
The RTL8305SB supports internal registers for individual ports for MAC to mask the current Link status from the PHY. For
example: If register EnPort0=0, MAC of port0 will ignore Link status from the PHY and treat this port as no-link.
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相關代理商/技術參數(shù) |
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| RTL8305SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:用于100M網(wǎng)絡交換 |
| RTL8305SC-LF | 制造商:Realtek Semiconductor 功能描述: |
| RTL8308B | 制造商:Realtek Semiconductor 功能描述:8-PORT 10/100 ETHERNET SWITCH CONTROLLER WITH EMBEDDED MEMORY, PQFP128 |
| RTL8309SB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| RTL8309SB-LF | 制造商:Realtek Semiconductor 功能描述:RTL8309 Series 9 Port 10/100 Mbps Ethernet Switch Controller - PQFP-128 制造商:Realtek 功能描述:RTL8309 Series 9 Port 10/100 Mbps Ethernet Switch Controller - PQFP-128 |
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