參數(shù)資料
型號(hào)： RTL8305SB
英文描述： RTL8305SB
中文描述： RTL8305SB
文件頁(yè)數(shù)： 44/66頁(yè)
文件大?。?/td> 963K
代理商： RTL8305SB
RTL8305SB
2002/04/09
44
Rev.1.0
7.3.5 SMI
The SMI (Serial Management Interface) is also known as the MII Management Interface, which consists of two signals
(MDIO and MDC), and allows external devices with SMI master mode (MDC is output) to control the state of the PHY and
internal registers (SMI slave mode: MDC is input). MDC is an input clock for the RTL8305SB to latch MDIO on its rising
edge. The clock can run from DC to 25MHz. MDIO is a bi-directional connection used to write data to, or read data from the
RTL8305SB. The PHY address is from 0 to 4.
SMI Read/Write Cycles
Preamble
(32 bits)
Start
(2 bits)
OP Code
(2 bits)
PHYAD
(5 bits)
REGAD
(5 bits)
Turn
Around
(2 bits)
Z0
10
Data
(16 bits)
Idle
Read
Write
1……..1
1……..1
01
01
10
01
AAAAA
AAAAA
RRRRR
RRRRR
D…….D
D…….D
Z*
Z*
Z*: high-impedance. During idle time, MDIO state is determined by an external 1.5K
pull-up resistor.
The RTL8305SB supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles without preamble bits.
However, for the first cycle of MII management after power-on reset, a 32-bit preamble is needed.
To guarantee the first successful SMI transaction after power-on reset, external device should delay at least 1sec to issue the
first SMI Read/Write Cycle relative to the rising edge of reset.
7.3.6 Head-Of-Line Blocking
The RTL8305SB incorporates an advanced mechanism to prevent Head-Of-Line blocking problem when flow control is
disabled. When the flow control function is disabled, the RTL8305SB will first check the destination address of the incoming
packet. If the destined port is congested, the RTL8305SB will discard this packet to avoid the blocking of the next packet,
which is going to a non-congested port.
7.3.7 802.1Q Port Based VLAN
The RTL8305SB supports five VLAN groups: VLAN A, B, C, D, and E. Two association ingress rules are provided to map a
frame to a given VLAN: port based and tagged-VID (VLAN Identifier).
Port based VLAN mapping is the simplest implicit mapping rule. A frame belongs to a VLAN is based on the index of the port
which it came from. P0VLANIndex[2:0], P1VLANIndex[2:0], P2VLANIndex[2:0], P3VLANIndex[2:0], and
P4VLANIndex[2:0] are used for each port as the distinguishing characteristic of a VLAN. Using the default value as an
example, P0VLANIndex[2:0]=0b000 means port 0 belongs to VLAN A. P1VLANIndex[2:0]=0b001 means port 1 belongs to
VLAN B. P2VLANIndex[2:0]=0b010 means port 2 belongs to VLAN C. P3VLANIndex[2:0]=0b011 means port 3 belongs to
VLAN D. P4VLANIndex[2:0]=0b100 means port 4 belongs to VLAN E.
The 12-bit tagged-VID is the explicit indication of the frame’s VLAN association. A total of 4094 values are possible. The
value of all ones (0xFFF) is reserved and currently unused. The value of all zero (0x000) indicates a priority tag. A priority
tagged frame is treated the same as an untagged frame. VIDA[11:0], VIDB[11:0], VIDC[11:0], VIDD[11:0], and VIDE[11:0]
are used as the distinguishing characteristic for each VLAN. For example, VIDA[11:0]=0x001 means frame with
tagged-VID=0x001 belongs to VLAN A. VIDB[11:0]=0x002 means frame with tagged-VID=0x002 belongs to VLAN B. VID
filed have no default values in the register, users must assign them in the serial EEPROM or register via SMI for the
Tagged-VID application.
Byte0~5
DA
Byte6~11
SA
Byte12~13
81-00
Byte14.7~14.5
User-Priority
( 0~3:Low-pri ; 4~7:
High-pri )
Byte14.4
CFI
0
Byte14.3~15.0
VID
Table 1: 802.1Q VLAN tag frame format
For the egress rule, each VLAN has a Member Set field. Member set of a VLAN indicates which ports belong to this VLAN.
Ports in the member set for a given VLAN can be expected to receive and transmit frames belonging to that VLAN; ports not
in the member set should generally not be receiving and/or transmitting frames for that VLAN. For the RTL8305SB, the
member set for a VLAN can be configured by serial EEPROM or register via SMI. Using the default value as an example,
MemberA[4:0]=10001 means port 4 and 0 are members of VLAN A. MemberB[4:0]=10010 means port 4 and 1 are members
of VLAN B. MemberC[4:0]=10100 means port 4 and 2 are members of VLAN C. MemberD[4:0]=11000 means port 4 and 3
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