參數(shù)資料
型號： RTL8305SB
英文描述： RTL8305SB
中文描述： RTL8305SB
文件頁數(shù)： 39/66頁
文件大?。?/td> 963K
代理商： RTL8305SB
RTL8305SB
2002/04/09
39
Rev.1.0
7.2 Physical Layer Functional Overview
7.2.1 Auto-Negotiation for UTP
The RTL8305SB obtains the states of duplex, speed and flow control ability through the auto-negotiation mechanism defined
in IEEE802.3u specifications for each port in UTP mode. During auto-negotiation, each port advertises its ability to its link
partner and compares ability with those received from its link partner. By default, the RTL8305SB advertises full capabilities
(100Full, 100Half, 10Full, 10Half) together with flow control ability.
7.2.2 10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven into the network media. The internal filter shapes
the driven signals to reduce EMI emission, eliminating the need for an external filter.
7.2.3 10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects the signal level is
above squelch level.
7.2.4 Link Monitor
The 10Base-T link pulse detection circuit always monitors the RXIP/RXIN pins for the presence of valid link pulses.
Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN signal pairs.
7.2.5 100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion,
and MLT3 encoding. The 5-bit serial data stream after 4B/5B coding is then scrambled as defined by the TP-PMD Stream
Cipher function to flatten the power spectrum energy such that EMI effects can be reduced significantly.
The scrambled seed is unique for each port based on PHY addresses. The bit stream after scrambler is driven into network
media in the form of MLT-3 signaling. The multi-level signaling technology moves the power spectrum energy from high
frequency to low frequency, which also benefits EMI emission.
7.2.6 100Base-TX Receive Function
The receive path includes a receiver composed of adaptive equalizer and DC restoration circuits to compensate for the
incoming distortion MLT-3 signal, MLT-3 to NRZI, NRZI to NRZ converter to convert analog signal to digital bit-stream , and
PLL circuit to clock data bit exactly with minimum bit error rate. De-scrambler, 5B/4B decoder and serial-to-parallel
conversion circuits are followed. Finally, the converted parallel data is fed into the MAC.
7.2.7 100Base-FX
All ports support 100Base-FX, which shares pins with UTP (TX+-/RX+-) and need no SD+- pins (Realtek patent). The
100Base-FX can be forced as half or full duplex with optional flow control ability. Hint: The 100Base-FX does not support
Auto-Negotiation according to IEEE 802.3u. In order to operate correctly, both sides of the connection should set the same
duplex and flow control ability. A scrambler is not needed in 100Base-FX. As compared to common 100Base-FX applications,
the RTL8305SB lacks of a pair of differential SD (signal detect) signals to achieve link monitoring function (Realtek patent),
which significantly reduces the pin count.
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