參數(shù)資料
型號(hào): S29PL032J70BAW13
廠商: SPANSION LLC
元件分類: PROM
英文描述: 2M X 16 FLASH 3V PROM, 70 ns, PBGA56
封裝: 7 X 9 MM, FBGA-56
文件頁(yè)數(shù): 84/100頁(yè)
文件大?。?/td> 967K
代理商: S29PL032J70BAW13
84
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A5 March 15, 2004
P R EL IMINAR Y
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 25 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE#
high to the data bus driven to VCC /2 is taken as tDF.
4. S29PL129J has two CE# (CE1#, CE2#).
5. Valid CE1# / CE2# conditions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) or (CE1# = VIH, CE2# = VIH)
6. Valid CE1# / CE2# transitions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) to (CE1# = CE2# = VIH)
7. Valid CE1# / CE2# transitions: (CE1# = CE2# = VIH) to (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL)
8. For 70pF Output Load Capacitance, 2 ns will be added to the above tACC,tCE,tPACC,tOE values for all speed grades
Table 27. Read-Only Operations
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
55
60
65
70
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
55
60
65
70
ns
tAVQV
tACC Address to Output Delay
CE#, OE# = VIL
Max
55606570
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
55606570
ns
tPACC Page Access Time
Max
20
25
30
ns
tGLQV
tOE
Output Enable to Output Delay
Max
20
25
30
ns
tEHQZ
tDF
Chip Enable to Output High Z (Note 3)Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Notes 1,
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 3)
Min
5
ns
tOEH
Output Enable Hold
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
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