參數(shù)資料
型號(hào)： S29PL032J70BAW13
廠商： SPANSION LLC
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 70 ns, PBGA56
封裝： 7 X 9 MM, FBGA-56
文件頁(yè)數(shù)： 96/100頁(yè)
文件大小： 967K
代理商： S29PL032J70BAW13
March 15, 2004 31107A5
S29PL127J/S29PL129J/S29PL064J/S29PL032J
95
PR EL IMINAR Y
Notes:
1. Typical program and erase times assume the following conditions: 25×C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90×C, VCC = 2.7 V, 100,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 21 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control
Table 34. Erase And Programming Performance
Parameter
Unit
Comments
Sector Erase Time
0.5
2
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
PL127J/129J
135
216
sec
PL064J
71
113.6
sec
PL032J
39
62.4
sec
Word Program Time
6
100
s
Excludes system level
overhead (Note 5)
Accelerated Word Program Time
460
s
Chip Program Time
PL127J/129J
50.4
200
sec
PL064J
25.2
50.4
sec
PL032J
12.6
25.2
sec
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6.3
7
pF
COUT
Output Capacitance
VOUT = 0
7.0
8
pF
CIN2
Control Pin Capacitance
VIN = 0
5.5
8
pF
CIN3
WP#/ACC Pin Capacitance
VIN = 0
11
12
pF
CE1#
tCCR
CE2#
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