參數(shù)資料
型號(hào)： S39421S
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Hot Swap Voltage Controller
中文描述： 電壓熱插拔控制器
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 201K
代理商： S39421S
S39421
7
2024 9.0 8/8/00
PIN DESCRIPTIONS
PIN NAME [CompactPCIname] (pin #)
VCC12 (Pin 1):
Supplies the 12 volts required for power-
ing the high-side drivers.
DRVREN (Pin 2):
Open drain, active low output indicates
the status of the 3 volt and 5 volt high side driver outputs
(VGATE5 and VGATE3). This signal may also be used as
a switching signal for the 12 volt supply.
ISLEW (Pin 3):
Diode-connected NFET input may be
used to adjust the 250V/s default slew rate of the high-side
driver outputs. One quarter of the current injected into this
pin will be mirrored into each of the high-side driver
outputs.
VSEL (Pin 4):
TTL level input used to determine which of
the Host power supply inputs will be monitored for valid
voltage and reset generation.
VSEL-Voltage
Select
Host Voltage
Monitored
Low
5 Volt or Mixed-Mode
High
3.3 Volt Only
DD (Pin 5):
A high going edge on this input will place the
embedded memory into Data Download mode. This
mode allows the entire contents of the E
2
PROM array to
be read out of the device by selecting the device (CS high)
and providing
clock cycles on the SK input. Data Down-
load mode is exited when Chip Select is brought low.
CS (Pin 6):
E
2
PROM memory chip select, active high.
SK (Pin 7):
E
2
PROM memory serial clock input.
DI (Pin 8):
E
2
PROM memory data input.
DO (Pin 9):
E
2
PROM memory data output.
PND2 [BD_SEL2#] (Pin 10):
Active low TTL level input
with internal pull-up to VCC5. In conjunction with PND1,
this signal indicates proper card insertion. This pin must
be connected to ground on the host side of the connector.
PND1 and PND2 must be placed on opposite corners of
the connector and will preferably be staggered shorter
than the power connector pins. Board insertion is as-
sumed when PND1 and PND2 are low.
PND1 [BD_SEL1#] (Pin 11):
Active low TTL level input
with internal pull-up to VCC5. In conjunction with PND2,
this signal indicates proper card insertion.
GND (Pin 12):
Ground.
CARD_V_VLD (pin13):
CARD_V_VLD is an open drain
output, indicating the card side voltages are at or above
V
TRIP
.
SGNL_VLD (Pin 14):
Signals valid (SGNL_VLD) is an
open drain active low signal indicating the card side power
is valid and that the reset signals have been released.
This signal can be used by the host as an indication that
the bus interface is active and all signals are valid.
HST_PWR (pin15):
The host power (HST_PWR) input is
an active high input. It provides the host system active
control over the sequencing of the power up operation.
When low, the S39421 will hold the add-in card in reset
and block all power to the backend logic. When
HST_PWR is high the power sequencing will begin imme-
diately and the reset outputs will be driven active after
t
PURST
.
HST_RST [PCI_RST#] (Pin 16):
TTL level input used as
a reset input signal from the host interface. An active low
level longer than 40 nsec will cause a reset sequence to
be performed on the card. The power switching logic will
not be affected.
RESET (Pin 17):
RESET is an active low open-drain
output. It should be tied high through a pull-up resistor
connected to V
CC
.
RESET (Pin 18):
RESET is an active high open drain
(PFET) output. It should be tied low through a pull-down
resistor connected to ground.
CARD_3V (Pin 19):
3.3 volt card side supply input. This
input is monitored for power integrity. If it falls below the
3.3V sense threshold, the PWR_VLD signal is de-as-
serted and a RESET sequence initiates.
VGATE3 (Pin 20):
Slew rate limited high side driver
output for the 3.3V external Power FET gate.
VCC3 (Pin 21):
3.3 volt host side supply input. This input
is monitored for power integrity. If it falls below the 3.3V
sense threshold, the SGNL_VLD signal is de-asserted
and the high side drivers disabled.
CARD_5V (Pin 22):
5 volt card side supply input. This
input is monitored for power integrity. If it falls below the
5V sense threshold and the VSEL input is low, the
PWR_VLD signal is de-asserted and a RESET sequence
initiates.
VGATE5 (Pin 23):
Slew rate limited high side driver
output for the 5V external Power FET gate.
VCC5 (Pin 24):
Power to the S39421 and 5 volt host side
supply input. This input is monitored for power integrity. If
it falls below the 5V sense threshold and the VSEL input
is low, the SGNL_VLD signal is de-asserted and the high
side drivers disabled.
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