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參數(shù)資料
| 型號： | S71GL064A08 |
| 廠商： | Spansion Inc. |
| 英文描述： | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品，閃存和RAM |
| 文件頁數(shù)： | 66/134頁 |
| 文件大小： | 2383K |
| 代理商： | S71GL064A08 |
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February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
35
Advance
Informatio n
Once the Secured Silicon Sector is programmed, locked and verified, the system must write
the Exit Secured Silicon Sector Region command sequence to return to reading and writing
within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and Protected At
the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped
from the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory
Locked device has an 16-byte random ESN at addresses 000000h–000007h. Please contact
your sales representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion pro-
gramming service (Customer Factory Locked). The devices are then shipped from the factory
with the Secured Silicon Sector permanently locked. Contact your sales representative for de-
tails on using the Spansion programming service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector
group without using VID. Write Protect is one of two functions provided by the WP#/ACC
input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase func-
tions in the first or last sector group independently of whether those sector groups were
protected or unprotected. Note that if WP#/ACC is at VIL when the device is in the standby
mode, the maximum input load current is increased. See the table in “DC Characteristics” sec-
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the
first or last sector was previously set to be protected or unprotected using the
method described in “Sector Group Protection and Unprotection”. Note that WP#
has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides
data protection against inadvertent writes (refer to Tables 16 and 17 for command defini-
tions). In addition, the following hardware data protection measures prevent accidental
erasure or programming, which might otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data
during VCC power-up and power-down. The command register and all internal program/erase
circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins
to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To ini-
tiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
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