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參數(shù)資料
| 型號： | S71GL064A08BFI0F3 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁數(shù)： | 49/134頁 |
| 文件大?。?/td> | 2383K |
| 代理商： | S71GL064A08BFI0F3 |
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February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
19
Advance
Informatio n
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are ini-
tiated through the internal command register. The command register itself does not occupy
any addressable memory location. The register is a latch used to store the commands, along
with the address and data information needed to execute the command. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and control levels
they require, and the resulting output. The following subsections describe each of these op-
erations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection
and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot
sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors will be protected or unprotected as determined by the
method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the factory (The Secured
Silicon Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL.
CE# is the power control and selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hard-
ware reset. This ensures that no spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to obtain array data. Standard mi-
croprocessor read cycles that assert valid addresses on the device address inputs produce
Operation
CE#
OE#
WE# RESET#
WP#
ACC
Addresses
(Note 1)
DQ0–DQ15
Read
L
H
X
AIN
DOUT
Write (Program/Erase)
L
H
L
H
(Note 3)
X
AIN
(Note 4)
Accelerated Program
L
H
L
H
(Note 3) VHH
AIN
(Note 4)
Standby
VCC ±
0.3 V
X
VCC ±
0.3 V
X
H
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
Sector Group Protect
(Note 2)
L
H
L
VID
H
X
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
(Note 4)
Sector Group
Unprotect
(Note 2)
L
H
L
VID
H
X
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L
(Note 4)
Temporary Sector
Group Unprotect
X
VID
H
X
AIN
(Note 4)
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