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| 型號(hào)： | S71GL064A08BFI0F3 |
| 廠(chǎng)商： | SPANSION LLC |
| 元件分類(lèi)： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁(yè)數(shù)： | 86/134頁(yè) |
| 文件大?。?/td> | 2383K |
| 代理商： | S71GL064A08BFI0F3 |
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February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
53
Advance
Informatio n
Write Operation Status
The device provides several bits to determine the status of a program or erase operation:
DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsections describe the function
of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase
operation is complete or in progress. The device also provides a hardware-based output sig-
nal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress
or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or
Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data#
Polling is valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the program address to read valid status in-
formation on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7
is active for approximately 1 s, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Em-
bedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data#
Polling produces a “1” on DQ7. The system must provide an address within any of the sectors
selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the un-
protected sectors, and ignores the selected sectors that are protected. However, if the system
reads DQ7 at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid data on DQ7. Depending on when the
system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0–
DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
gorithm. Figure 19 in the AC Characteristics section shows the Data# Polling timing diagram.
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| S71GL064A08BFW0B0 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
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| S71GL064A08BFW0F0 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| S71GL064A08BFW0F2 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
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